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lecture_03 - ECE 190 Lecture 03 Digital Logic Structures I...

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ECE 190 Lecture 03 August 30, 2011 1 V. Kindratenko Digital Logic Structures - I Lecture Topics MOS devices Gates Combinational logic Storage elements Lecture materials Textbook § 3.1-3.4 Homework/Projects HW1 posted on the course website (http://courses.engr.illinois.edu/ece190/) HW1 due Wednesday August 31 at 5pm in the ECE190 drop box located in the basement of Everitt Lab Announcements Getting credit in James Scholar Honors Program o Prof. Steve Lumetta will be administering James Scholar work this semester. o The work will involve programming a mobile platform (smartphone) o If interested, contact Prof. Lumetta directly Class Committee Class committee will be setup to serve as a communication channel between the students taking ECE 190 and the teaching staff. Class committee meets with the teaching staff every other week. o Meeting schedule TBD If you have any questions or concerns that you would like the class committee to discuss during the upcoming meeting, please send them either to one of the instructors to one of the class committee members. If you would like to serve on the Class Committee, please email Prof. Kindratenko
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ECE 190 Lecture 03 August 30, 2011 2 V. Kindratenko MOS devices Today’s computers are made of MOS transistors o MOS FETs metal-oxide semiconductor field-effect transistors o For the purpose of this course, we will treat MOS FETs as simple switching devices, or electrically controlled switches o Switch-based circuits can easily represent two states: on/off, open/close, voltage/no voltage Two types of MOS FETs o n -type Terminal 3 is called gate Terminal #2 must be connected to the ground o p -type terminal #1 must be connected to a positive supply voltage source (Vdd) Concept of Voltage o GND reference voltage, 0 V We will refer to 0 V as a digital value of 0 o Vdd positive supply voltage of a FET, ~1 V We will refer to Vdd V as a digital value of 1 MOS FETs as electrically controlled switches o n -type Attached to GND when Gate has positive voltage, short circuit between #1 and #2 (switch closed) when Gate has zero voltage, open circuit between #1 and #2 (switch open) Pulls output voltage DOWN when input is one n
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