# lecture_04 - ECE 190 Lecture 04 September 1 2011 Digital...

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ECE 190 Lecture 04 September 1, 2011 1 V. Kindratenko Digital Logic Structures - II Lecture Topics Storage elements Memory Sequential logic FSM Lecture materials Textbook § 3.4 – 3.7 Homework/Projects HW2 due September 7 at 5pm in the ECE 190 drop-off box Announcements Lab 2 is tomorrow. Labs will be released on Wednesdays. You are welcome to start working on them as soon as they are released, no need to wait until Friday. Labs are due on Fridays at 7pm.

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Lecture 04 September 1, 2011 2 V. Kindratenko Storage elements Gated D latch Gated D latch allows to work with the R-S latch storage element in a more “controlled” way, avoiding the situation when both s and r inputs are set to 0. It consists of an R-S latch with two additional NAND gates put in front of it: here input “ we ” stand for write-enable, input “ d ” stands for data value, and output “ q ” stands for latch output o when we =0, s and r inputs to the R-S latch are set to 1, and the value stored in latch persists o when we =1 and d =0: s =1 and r =1, and thus q =0 – R-S latch stores value 0 o when we =1 and d =1: s =0 and r =1, and thus q =1 – R-S latch stores value 1 We will use the following symbolic representation for gated D latch: or Register A structure that can be used to store a group of bits o Example: 4-bit register made of four D-latches, all controlled by a common WE. o
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lecture_04 - ECE 190 Lecture 04 September 1 2011 Digital...

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