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lecture_07 - ECE 190 Lecture 07 LC-3 ISA II Lecture Topics...

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ECE 190 Lecture 07 September 13, 2011 1 V. Kindratenko LC - 3 ISA - II Lecture Topics LC-3 data movement instructions LC-3 control instructions Lecture materials Textbook § 5.3 - 5.6 Textbook Appendix A.3 Homework/Projects HW3 due this Wednesday Put your name, lab section number, netid on the HW3, otherwise we will not grate it. HW1-2 re-grade requests are due this Friday. HW3 re-grade requests are due next Friday. We will not accept re-grade requests for HWs past next Friday. MP1 is already released, due next Wednesday. Announcements Exam 1 is on Mon, Sept. 26 , 7-10pm Let us know if you have a conflict by next Wednesday
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ECE 190 Lecture 07 September 13, 2011 2 V. Kindratenko LC-3 data movement instructions Load instruction using base + offset addressing mode (LDR) Operation: the content of memory at the address computed as the sum of the address stored in the base address register (BaseR) and the sign-extended last 6 bits of the instruction (offset6) is loaded into the destination register (DR) o DR mem[BaseR+SEXT(offset6)] o setcc Encoding: 0 opcode 1 1 0 destination register offset6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LDR base address register Datapath relevant to the execution of this instruction: o Example: 0110 001 010 011101; LDR R1, R2, offset xABCD x2345 R0 R1 R2 R3 R4 R5 R6 R7 ADD 0 1 1 0 0 0 1 0 1 0 0 1 1 1 0 1 IR 6 DR 3 SEXT IR[5:0] 16 xABCD MDR MAR 16 16 x1D x2362 x2362 BaseR 3 1 0 0 N Z P MAR R2 + SEXT(IR[5:0]) MDR mem[MAR]
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ECE 190 Lecture 07 September 13, 2011 3 V. Kindratenko R1 ← MDR offset6 field is 6-bit wide, thus the offset can be from -32 to +31 Store instruction using base + offset addressing mode (STR) Operation: value stored in the source register (SR) is transferred to the memory at the address computed as the sum of the address stored in the base address register (BaseR) and the sign- extended last 6 bits of the instruction (offset6) o mem[BaseR+SEXT(offset9)] ← SR Encoding: 0 opcode 1 1 1 source register offset6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STR base address register Datapath relevant to the execution of this instruction: o Example: 0111 001 010 011101; STR R1, R2, offset xFEDC x2345 R0 R1 R2 R3 R4 R5 R6 R7 ADD 0 1 1 1 0 0 1 0 1 0 0 1 1 1 0 1 IR 6 SR 3 SEXT IR[5:0] 16 xFEDC MDR MAR 16 16 x1D x2362 x2362 BaseR 3 MAR R2 + SEXT(IR[5:0]) MDR R1
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ECE 190 Lecture 07 September 13, 2011 4 V. Kindratenko mem[MAR]
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