Lect_05 - ECE 342 Jose Schutt Aine ECE 442 Solid State...

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Unformatted text preview: ECE 342 Jose Schutt Aine ECE 442 Solid State Devices & Circuits 5. CMOS Logic Circuits Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 ECE 342 Jose Schutt Aine Digital Logic - Generalization De Morgans Law ... ... A B C A B C + + + = ... ... A B C A B C = + + + General Procedure 1. Design PDN to satisfy logic function 2. Construct PUN to be complementary of PDN in every way 3. Optimize using distributive rule Distributive Law ( ) ( ) AB AC BC BD A B C B C D + + + = + + + 2 ECE 342 Jose Schutt Aine PUN conducts when inputs are low and consists of PMOS transistors PDN consists of NMOS transistors and is active when inputs are high PDN and PUN utilize devices In parallel to form OR functions In series to form AND functions Two Networks Pull-down network (PDN) with NMOS Pull-up network (PUN) with PMOS CMOS Logic Gate Circuits 3 ECE 342 Jose Schutt Aine Pull-Down Networks Y A B = + Y A B = 4 ECE 342 Jose Schutt Aine Pull-Up Networks Y A B = + Y A B = 5 ECE 342 Jose Schutt...
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Lect_05 - ECE 342 Jose Schutt Aine ECE 442 Solid State...

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