Lect_18 - ECE ECE442 SolidStateDevices&Circuits...

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CE 442 ECE 442 Solid State Devices & Circuits 18. Advanced Techniques Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 Jose E. Schutt Aine ECE 442
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Darlington Configuration - Popular BJT combination -C o m posite transistor with = 1 2 - Can be used as the ascade of two CC cascade of two CC 2 Jose E. Schutt Aine ECE 442
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Darlington Voltage Follower      12 2 11 in e e E Rr r R     /1  es i g tE rR R r 2 2 // 1  ou e RR t  2 out E i g sig Ee v R v 2 1  3 Jose E. Schutt Aine ECE 442
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Darlington Voltage Follower Darlington follower presents high input impedance 4 Jose E. Schutt Aine ECE 442
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Darlington Voltage Follower 1 r r R  Input impedance      12 2 11 in e e E Rr    /( 1) //  es i g ut E e rR RR r Output impedance 2 2 1   out Voltage gain: 21 1 2 /( 1) /( E MB E ee s i g R A 5 Jose E. Schutt Aine ECE 442
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Op Amp Architecture Concepts - Many op amps consist of 3 amplifying stages - The first stage is always a high-gain differential stage - The second stage has moderate value of voltage gain - The last stage is often a buffer stage with high current gain and voltage gain near unity - The high-frequency poles of each stage introduce phase shift at higher frequencies may lead to scillations 6 Jose E. Schutt Aine ECE 442 oscillations
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Op Amp Specifications Specifications - Input Offset Voltage ( V os ) - Input Offset Voltage Drift ( TCV os ) put Bias Current ( - Input Bias Current ( I B ) - Input Offset Current ( I os ) - Common-Mode Input Voltage Range ( CMVR ) - Common-Mode Rejection Ratio ( CMRR ) - Power Supply Rejection Ratio ( PSRR ) 7 Jose E. Schutt Aine ECE 442
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CMOS OP Amp Example In the differential amplifier shown, Q 1 and Q 2 form the differential pair while the current source transistors Q 4 and Q 5 form the active ads for d spectively The dc bias circuit that establishes loads for Q 1 and Q 2 respectively. The dc bias circuit that establishes an appropriate dc voltage at the drains of Q 1 and Q 2 is not shown. The following specifications are desired: differential gain A d = 80V/V, I REF = 100 A, the dc voltage at the gates of Q 6 and Q 3 is +1.5V; the dc voltage at the gates of Q 7 , Q 4 and Q 5 is –1.5V. The technology available is specified as follows: n C ox =3 p C ox = 90 A/V 2 ; V tn =|V tp | =0.7V, V An =|V Ap | = 20V. Specify the required value of R and the W/L ratios for all transistors. Also, specify I D and V GS at which each transistor is operating. For dc bias calculations, you may neglect channel-length modulation. Fill in e entries in the table provided to show your results 8 Jose E. Schutt Aine ECE 442 the entries in the table provided to show your results.
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CMOS OP Amp Example 9 Jose E. Schutt Aine ECE 442
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CMOS OP Amp Example 1.5 ( 1.5) 3 100 30 0.1 REF V I AR k Rm A   
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Lect_18 - ECE ECE442 SolidStateDevices&Circuits...

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