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Final%20Project

# Final%20Project - VLSI design of 4-bit Synchronous...

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VLSI design of 4-bit Synchronous counter (VLSI DESIGN PROJECT EE - 4242) By SUMAN KUMAR PRADEEP KHANAL KHALEF HOSANY BIN FU Submitted To Prof. Ashok Srivastava FALL 2004 DEPARTMENT OF ELECTRICAL ENGINEERING LOUISIANA STATE UNIVERSITY

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Contents 1. Objective 2. Project Description 2.1 Problem Definition 2.2 Design Methodology 3. Logic Design 3.1 Inverter 3.2 NAND Gate 3.3 S-R Latch and its Truth Table 3.4 Master Slave JK Flip Flop and its Truth Table 3.5 Full Logic Level Block Diagram 4. CMOS Implementation in L-Edit and Spice Simulations 4.1 Inverter 4.2 NAND Gate 4.3 S-R Latch 4.4 Master Slave J-K Flip-Flop 4.5 4-bit Synchronous Binary Counter 4.6 Pad Frame with I/O Pin Numbers 5. Testing Procedures 6. Conclusion 7. Appendix 7.1 Inverter .CIR File 7.2 NAND Gate .CIR File 7.3 S-R Latch .CIR File 7.4 Master Slave J-K Flip-Flop .CIR File 7.5 4-Bit Synchronous Counter .CIR File
1. Objective : To design a 4-bit synchronous counter using Master Slave JK FlipFlops and implement it using L-edit layout design in CMOS technology. 2. Project Description: 2.1 Problem Definition: A 4-bit binary counter is used to count from 0 to 15 in binary. In order to achieve this, 16 different logic states are needed and this can be obtained by using a combination of 4 flipflops. The circuit has 1 input to enable the counter and 1 input for the clock. The output of the 4 flipflops corresponds to the current state of the counter, and at every clock pulse the counter moves into the next stage, as shown in the state diagram below: State Diagram for 4-bit binary counter Thus the circuit counts from 0000 to 1111 and repeats itself. The design of the counter was implemented using CMOS technology in L-edit. 011 1 011 0 111 1 000 0 000 1 001 0 001 1 010 0 110 1 110 0 101 1 101 0 111 0 100 1 010 1 100 0

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2.2 Design methodology: Methodology: CMOS Design Software L-Edit Version 9.1 Logic Level Software B^2 Logic Version 3.0 Circuit Simulation Software Cadence PSPICE Version 10.0 Technology used Scalable CMOS N-WELL Technology Design Rule followed Mosis 1.5 – Micron minimum Feature size Technology Parameter 1 Internal unit=0.5 Lambda 1 Lambda=0.8 Micron Minimum transistor Dimensions N-MOS: L= 1.6 microns, W=2.4 microns P-MOS: L= 1.6 microns, W=4.8 microns Apart from the above, the following points were also kept in mind while designing the circuit and logic gates: The circuit was optimized to ensure that the minimum number of transistors was used. A building block approach was used to generate the final Circuit. Basic cells were created and optimized and then instanced and used to generate more complex cells, until the final counter was obtained. The final circuit was optimized for minimum space usage on the padframe. The resistivity of the circuit was minimized by limiting the use of high resistance
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Final%20Project - VLSI design of 4-bit Synchronous...

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