Chapter 4

Chapter 4 - Machine Language Native binary code that the...

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Machine Language ± Native binary code that the microprocessor understand and uses as its instructions to control its operation. ± Their length vary from 1 to 13 bytes. ± The instructions for the 8086 through the 80286 have the format shown below. Opcode MOD-REG-R/M Displacement Immediate 1 to 2 bytes 0 to 1 byte 0 to 1 byte 0 to 2 bytes Address size Operand size Opcode MOD-REG-R/M Scaled index Displacement Immediate 0 to 1 bytes 0 to 1 bytes 1 to 2 bytes 0 to 1 byte 0 to 1 byte 0 to 4 bytes 0 to 4 bytes
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Machine Language ± The Opcode selects the operation to be performed by the microprocessor. ± The remaining two bits indicate: ² D – direction of flow of information: ± D=0: R/M REG; ± D=1: REG R/M. ² W – Size of data: ± W=0: Byte; ± W=1: Word, Doubleword . DW Opcode
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Machine Language ± MOD field specifies the addressing mode for the selected instruction. ± REG field indicates a register. ± R/M field indicates either a register MOD=11, or a memory addressing mode. MOD REG R/M
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Machine Language MOD Function 00 No displacement 01 8 bit sign extended displacement 10 16/32 bit displacement 11 R/M is a register W = 0 REG Byte Word Doubleword 000 AL AX EAX 001 CL CX ECX 010 DL DX EDX 011 BL BX EBX 100 AH SP ESP 101 CH BP EBP 110 DH SI ESI 111 BH DI EDI W = 1 R/M Addressing Mode 000 DS:[BX+SI] 001 DS:[BX+DI] 010 SS:[BP+SI] 011 SS:[BP+DI] 100 DS:[SI] 101 DS:[DI] 110 SS:[BP] 111 DS:[BX]
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Push/Pop ± PUSH source ² Reg16, reg32; ² Mem16, mem32; ² Seg; ² Imm8, imm16, imm32; ± PUSHA – all 16 bit registers. ± PUSHAD – all 32 bit registers. ± PUSHF – flags. ± PUSHFD – extended flags.
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Push/Pop ± POP source ² Reg16, reg32; ² Mem16, mem32; ² Seg; ² Imm8, imm16, imm32; ± POPA – all 16 bit registers. ± POPAD – all 32 bit registers. ± POPF – flags. ± POPFD – extended flags.
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Stack Initialization ± Load both: ² The stack segment register (SS); ² The stack pointer (SP).
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Load-effective Address ± LEA – loads a 16 or 32 bits register with the address of the data specified. ² LEA EBX,ARRAY ± The OFFSET directive does the same thing. ² MOV EBX,OFFSET ARRAY ± LDS, LES, LFS, LGS, and LSS loads a 16 or 32 bits register with an offset address and DS, ES, FS, GS, and SS with a segment address.
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Load-effective Address ± LDS, LES, LFS, LGS, and LSS loads a 16 or 32 bits register with an offset address and DS, ES, FS, GS, and SS with a segment address. ² LDS SI,MESS
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String Instructions ± String instructions were designed to operate on large data structures. ± The SI and DI registers are used as pointers to the data structures being accessed or manipulated. ± The operation of the dedicated registers stated above are used to simplify code and minimize its size.
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String Instructions ± The registers(DI,SI) are automatically incremented or decremented depending on the value of the direction flag: ² DF=0, increment SI, DI.
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This note was uploaded on 01/25/2012 for the course EE 3750 taught by Professor Desouza during the Fall '08 term at LSU.

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Chapter 4 - Machine Language Native binary code that the...

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