test #1 spring 2002

test #1 spring 2002 - F = 50. 5.) Compute the power...

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 Name:_________________________________________ EE 3220 Test #  1 Spring  2002 SSN:__________________________________________  DO NOT WRITE ON THE BACK OF THESE PAGES. 1.) Perform the DC bias analysis for the circuit below.  (Find all node voltages and  currents).  What is the power absorbed by the transistor? 2.) Draw the complete small signal model for the circuit below and derive the gain  v o /v s . Assume C E  and C S  have negligible impedances in the small signal model.
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3.) For the circuit below, what is the largest voltage that will still have the transistor  operating in the constant current region 4.) Choose a value for R C  that will bias the transistor approximately half way  between saturation and cutoff.  Assume V SAT  is 0.2 V and 
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Unformatted text preview: F = 50. 5.) Compute the power delivered to the load for this cascaded amplifier network. How could the power delivered be improved further? 6.) What are the advantages and disadvantages of adding a resistor to the emitter of a BJT amplifier? 7.) Why is using a bypass capacitor across the emitter resistor in a single BJT amplifier not a viable IC solution? 8.) What uncontrollable factors affect F of a BJT? 9.) Find the output swing range for the differential amplifier. (You will need to solve for I O first.) 10.) Approximate the single ended differential and common mode gain at output 1 (A dm-se1 and A cm-se1 ) for the differential amplifier circuit of problem # 9....
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test #1 spring 2002 - F = 50. 5.) Compute the power...

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