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test #1 summer 2001

# test #1 summer 2001 - circuit below 5 Compute the power...

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Name:_________________________________________ EE 3220 Test #  1 Summer 2001 SSN:__________________________________________  DO NOT WRITE ON THE BACK OF THESE PAGES. 1.) Perform the DC bias analysis for the circuit below.  (Find all node voltages and  currents).  What is the power absorbed by the transistor? 2.) Draw the complete small signal model for the circuit below and derive the gain  v o /v s . Assume C E  and C S  have negligible impedances in the small signal model.

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3.) For the circuit below, what is the largest voltage that will still have the transistor  operating in the constant current region?  Draw the transfer characteristic (v o /v s for the circuit. 4.) Use the small signal model to compute the input and output impedance for the

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Unformatted text preview: circuit below. 5.) Compute the power delivered to the load for this cascaded amplifier network. How could the power delivered be improved further? 6.) Choose a value for R C and R E that will bias V C close to 0 volts and have a small signal gain of at least 3. 7.) Sketch the output for the circuit below given the input signal v s applied. Label all important points. 8.) Explain the advantage of using a BJT (with a resistive load) for signal amplification over an FET with a resistive load. 9.) What are the advantages and disadvantage of adding a resistor to the emitter of a BJT amplifier? 10.) What uncontrollable factors affect β F of a BJT?...
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