NC State University ECE 546 Fall 2011 ECE Department VLSI Systems Design W. Rhett Davis Homework #2 Tutorials Work through the Layout Tutorial #1 – Introduction to Layout and DRC(found on the “Tool Tips” section of the course web-page) to learn how to create layout with Cadence. Problems 1.Inverter Layout and Delay a.Following the tutorial, create the layout for a CMOS inverter with Wn/Ln= 90nm/50nm, Wp/Lp= 180nm/50nm. Turn in a print-out of your layout. b.Derive values for all parasitic capacitances using the hand-analysis parameters (on the course web-page) for both the low-high and high-low transitions. Assume VDD=1.0 V. c.Find tpLHand tpHLfor this basic inverter. Assume that the inverter is loaded with an identical inverter. You may reference the values of Reqnand Reqpfrom HW#1. d.What is the maximum fan-out of identical inverters this gate can drive before its delay becomes larger than 50ps? e.Find tpLHand tpHLfor this inverter using a transient simulation in HSPICE.
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English-language films, Following, inverter, energy consumption