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hw3 - out A 15 fF 5 fF 3 Elmore Delay Find the RC...

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NC State University ECE 546 Fall 2011 ECE Department VLSI Systems Design W. Rhett Davis Homework #3 Problems 1. Driving Large Capacitances You are designing a chain of inverters to drive a capacitance of 1 pF in the minimum time. Assume t p0 =5 ps, C in1 =0.5 fF, and =1.1. a. Find the theoretical optimum fan-out (f) to drive this capacitance. b. Find the minimum total delay to drive this capacitance with 4 stages. 2. Cross-Talk Delay-Noise Find the t pHL at node “out” for the inverter shown below, assuming that node “A” has the waveform shown. Assume that R eq for the inverter is 5 k and that node “out” begins its transition at time=0.
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Unformatted text preview: out A 15 fF 5 fF 3. Elmore Delay Find the RC propagation delay from the output of gate 1 to the input of gate 2. Assume that all gates have an input capacitance of 10 fF and an output capacitance of 5 fF. Assume that the wire is a one-sided minimum-width metal-4 wire over field oxide and that the equivalent resistance of gate 1 is 1k . Use a model for each wire-segment and the Elmore approximation to find the delay. Use the parasitic capacitances and resistances given in the hand-analysis parameters posted on the course web-page. Gate 1 Gate 2 Gate 3 1 mm 1 mm 2 mm 1 mm 1 mm Gate 4...
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