hw4 - c. Calculate t pHL and t pLH for this gate, assuming...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
NC State University ECE 546 Fall 2011 ECE Department VLSI Systems Design W. Rhett Davis Homework #4 Tutorials Work through Layout Tutorial #2 – LVS and Parasitic Extraction using Calibre (found on NCSU Cadence Wiki Tutorial Page). Note that this tutorial has not yet been updated to the latest design rules, so your layout should be more dense than the one shown. Problems 1. Circuit from Logic Function, Sizing, and Capacitance a. For the logic function   DE C B A F , Sketch the complete complementary CMOS circuit. Then size it for a 10k maximum resistance to VDD or GND (Assume a 90/50 NMOS has 10k resistance and that of the PMOS is 2X higher). Assume that you have complemented signals as inputs, if needed. b. Consider the gate given below. Without calculating t pHL and t pLH for this gate, predict the input transitions that are likely to result in the largest values for each delay.
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: c. Calculate t pHL and t pLH for this gate, assuming that C L =2 fF. Follow the method in example 6.4 and table 6-3 in your text, but assume that C GD , C GS , C DB , and C SB are each 1 aF per nm of gate width (for simplicity). Assume the following input transitions: t pHL : t pLH : 2. Euler Paths and Stick Diagram for Standard Cells For the logic function in problem 2 above, a. Draw the logic diagram b. Determine the consistent Euler paths for the PUN and PDN c. Sketch the stick diagram for the circuit 3. Layout Tutorial #2 Include your final extracted SPICE files ( NAND2.pex.netlist , NAND2.pex.netlist.pex , and NAND2.pex.netlist.NAND2.pxi ) and LVS report ( NAND2.lvs.report ) in your solution document....
View Full Document

Ask a homework question - tutors are online