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Unformatted text preview: c. Calculate t pHL and t pLH for this gate, assuming that C L =2 fF. Follow the method in example 6.4 and table 6-3 in your text, but assume that C GD , C GS , C DB , and C SB are each 1 aF per nm of gate width (for simplicity). Assume the following input transitions: t pHL : t pLH : 2. Euler Paths and Stick Diagram for Standard Cells For the logic function in problem 2 above, a. Draw the logic diagram b. Determine the consistent Euler paths for the PUN and PDN c. Sketch the stick diagram for the circuit 3. Layout Tutorial #2 Include your final extracted SPICE files ( NAND2.pex.netlist , NAND2.pex.netlist.pex , and NAND2.pex.netlist.NAND2.pxi ) and LVS report ( NAND2.lvs.report ) in your solution document....
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- Fall '11