# hw5 - NC State University ECE Department ECE 546 VLSI...

This preview shows pages 1–2. Sign up to view the full content.

NC State University ECE 546 Fall 2011 ECE Department VLSI Systems Design W. Rhett Davis Homework #5 Problems 1. Combinational Logic Sizing with Logical Effort You are designing a circuit with an unfamiliar gate. Simulation of the gate and a minimum-sized inverter yield the graph below. Simulations also show that the input capacitance of the unfamiliar gate is 30 fF, and for the inverter is 5 fF. Assume that the ratio of internal to input capacitance ( ) is 1 for this problem. a. What is t p0 for this logic family? b. What are intrinsic delay coefficient (p) and logical effort (g) for this gate? c. You would like to use the unfamiliar gate in the circuit below and size all of the gates for minimum path delay. Find the effective fanout needed for the unfamiliar gate. 2. Pseudo NMOS For the Pseudo NMOS circuit to the left a. Calculate V OL and V OH ., assuming that only one of the inputs (A or B) is high. You may use the modified equation (6.28) from Lecture 10, slide 9. Be sure to show that the assumed region of operation is correct.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

## This note was uploaded on 01/26/2012 for the course EE 546 taught by Professor Whett during the Fall '11 term at N.C. State.

### Page1 / 2

hw5 - NC State University ECE Department ECE 546 VLSI...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online