ece546fall11_06

ece546fall11_06 - ECE ECE 546 - VLSI Systems Design Lecture...

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ECE 546 ECE 546 - VLSI Systems Design VLSI Systems Design ecture ecture : Sizing for Large Loads : Sizing for Large Loads Lecture Lecture 6: Sizing for Large Loads, 6: Sizing for Large Loads, Wire Extraction & Delay Fall Fall 2011 2011 W. Rhett Davis NC State University ith significant material from ith significant material from abaey abaey handrakasan handrakasan and and ikoli ć Slide 1 © W. Rhett Davis NC State University ECE 546 Fall 2011 with significant material from with significant material from Rabaey Rabaey, , Chandrakasan Chandrakasan, and , and Nikoli Nikoli
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Announcements HW#2 Due Today HW Deadline moved to 11:45pm No Peer Grading for HW#2 HW#3 Due in 1 Week Slide 2 © W. Rhett Davis NC State University ECE 546 Fall 2011
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Summary of Last Lecture What are the different components of the ffective load capacitance (C for an inverter effective load capacitance (C L ) for an inverter loaded with an identical inverter? What is the best way to choose the ratio = r an Inverter? W p /W n for an Inverter? Slide 3 © W. Rhett Davis NC State University ECE 546 Fall 2011
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Today’s Lecture riving Large Capacitances Driving Large Capacitances (5.4.3) Extracting Wire Capacitances (4.1 – 4.3.2) » Classical (inter-layer area + fringe) » Modern (intra-layer coupling) » Cross-Talk Delay Noise Slide 4 © W. Rhett Davis NC State University ECE 546 Fall 2011
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Inverter Chain In Out C L If C L is given: - How many stages are needed to minimize the delay? - How to size the inverters? May need some additional constraints. Slide 5 © W. Rhett Davis NC State University ECE 546 Fall 2011
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Inverter Delay • Unit Inverter • Minimum length devices, L=50 nm •W N =W unit , W P = const* W unit (e.g. const= 2 ) • same pull-up and pull-down currents • approx. equal resistances R N = R P = R unit • output capacitance C unit pprox equal rise nd fall elays 2 W approx. equal rise t pLH and fall t pHL delays • Larger Inverters • s = size W • W N =s*W unit , W P = s*const*W unit •R N = R P = R S = R unit (W unit /W N ) = R unit /s • output (internal) capacitance C t = C nit (W /W nit ) = C nit *s Slide 6 © W. Rhett Davis NC State University ECE 546 Fall 2011 int unit N unit unit • Delay = t p = 0.69 R S (C int +C L )
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Inverter with Load Delay 2 W C int C L W Load Delay = 0.69 R S ( C int + C L ) = 0.69 R S C int + 0.69 R S C L = 0.69 R C t (1+ C / C t ) Slide 7 © W. Rhett Davis NC State University ECE 546 Fall 2011 S int L int = Delay (Internal) + Delay (Load)
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Delay Formula elay   ~ C C R Delay L int S     / 1 / 1 69 . 0 0 int f t C C C R t p int L S p C int = C in with  1 (1.1 in our process) f = C L /C in - effective fanout R R S = R unit /s C int = C unit *s t p 0 = 0.69 R unit C unit Slide 8 © W. Rhett Davis NC State University ECE 546 Fall 2011
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Apply to Inverter Chain In Out C L 1 2 N t = t + t + …+ t p p 1 p 2 pN j gin unit unit pj C C R t 1 , 1 ~ j gin C , in N j gin N C C C t t t 1 , , 1 Slide 9 © W. Rhett Davis NC State University ECE 546 Fall 2011 L N gin i j gin p j j p p C 1 , 1 , 0 1 ,
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This note was uploaded on 01/26/2012 for the course EE 546 taught by Professor Whett during the Spring '11 term at N.C. State.

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ece546fall11_06 - ECE ECE 546 - VLSI Systems Design Lecture...

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