ece546fall11_07

ece546fall11_07 - ECE ECE 546 - VLSI Systems Design Lecture...

Info iconThis preview shows pages 1–10. Sign up to view the full content.

View Full Document Right Arrow Icon
ECE 546 ECE 546 - VLSI Systems Design VLSI Systems Design ecture ecture : Wire Extraction & Delay : Wire Extraction & Delay Lecture Lecture 7: Wire Extraction & Delay, 7: Wire Extraction & Delay, Complementary CMOS Fall Fall 2011 2011 W. Rhett Davis NC State University ith significant material from ith significant material from abaey abaey handrakasan handrakasan and and ikoli ć Slide 1 © W. Rhett Davis NC State University ECE 546 Fall 2011 with significant material from with significant material from Rabaey Rabaey, , Chandrakasan Chandrakasan, and , and Nikoli Nikoli
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Announcements HW#3 Due Tuesday Cover Sheet for HW#3 Posted lease put your answers in the cover (Please put your answers in the cover sheet) Slide 2 © W. Rhett Davis NC State University ECE 546 Fall 2011
Background image of page 2
Summary of Last Lecture How do you size a chain of inverters to drive a large load with minimum delay? How do you find the optimum number of stages to drive a large load? How do you determine parasitic wire capacitance? ow do you model cross- lk delay- oise? Slide 3 © W. Rhett Davis NC State University ECE 546 Fall 2011 How do you model cross talk delay noise?
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Today’s Lecture xtracting Wire Resistance Extracting Wire Resistance (4.3.2) Estimating Delay of Interconnect (4.4 – 4.4.4, 4.5.2) Complementary CMOS Gates (6.1 – 6.2.1) Slide 4 © W. Rhett Davis NC State University ECE 546 Fall 2011
Background image of page 4
Wire Resistance R = H W L L H Sheet Resistance R o R W R 1 R 2 Slide 5 © W. Rhett Davis NC State University ECE 546 Fall 2011
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Interconnect Resistance Slide 6 © W. Rhett Davis NC State University ECE 546 Fall 2011
Background image of page 6
Dealing with Resistance Selective Technology Scaling Use Better Interconnect Materials » reduce average wire-length » e.g. copper, silicides ore Interconnect Layers More Interconnect Layers » reduce average wire-length Slide 7 © W. Rhett Davis NC State University ECE 546 Fall 2011
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Polycide Gate MOSFET Silicide PolySilicon + + SiO 2 n n p Silicides: WSi 2, TiSi 2 , PtSi 2 and TaSi Conductivity: 8-10 times better than Poly Slide 8 © W. Rhett Davis NC State University ECE 546 Fall 2011
Background image of page 8
Layer Stack Layer Pitch (Width/Space) (nm) Thick.
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 10
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 36

ece546fall11_07 - ECE ECE 546 - VLSI Systems Design Lecture...

This preview shows document pages 1 - 10. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online