ece546fall11_09

ece546fall11_09 - ECE ECE 546 - VLSI Systems Design Lecture...

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ECE 546 ECE 546 - VLSI Systems Design VLSI Systems Design ecture ecture : : Lecture Lecture 9: 9: Logical Effort Fall Fall 2011 2011 W. Rhett Davis NC State University ith significant material from ith significant material from abaey abaey handrakasan handrakasan and and ikoli ć Slide 1 © W. Rhett Davis NC State University ECE 546 Fall 2011 with significant material from with significant material from Rabaey Rabaey, , Chandrakasan Chandrakasan, and , and Nikoli Nikoli
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Announcements HW#4 Due Tuesday » Problem 1: Note change in function (posted today at 1:30pm) – Prob. 1a decoupled from 1b and 1c Slide 2 © W. Rhett Davis NC State University ECE 546 Fall 2011
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Summary of Last Lecture How are logic diagrams useful? How do you choose the order of polysilicon lines to get an optimally small layout for a omplex gate? complex gate? What are some of the methods to improve the performance of a Complementary CMOS gate? Slide 3 © W. Rhett Davis NC State University ECE 546 Fall 2011
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Today’s Lecture ogical Effort Logical Effort (6.2.1) Slide 4 © W. Rhett Davis NC State University ECE 546 Fall 2011
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Sizing a Logic Chain In Out C L If C L is given: - How to size the inverters? - How to generalize for arbitrary logic gates? Slide 5 © W. Rhett Davis NC State University ECE 546 Fall 2011
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Summary of Inverter Sizing Sizing a chain of verters inverters » single stage delay =C int /C in 0.75 f = C L /C in for stage   / 1 0 f t t p p NEXT: Generalize this approach for a chain of rbitrary CMOS gates » multi-stage delay   / 1 N F Nt t arbitrary CMOS gates driving a large capacitance – N = no. of stages –F = C L / C in for chain 0 p p Slide 6 © W. Rhett Davis NC State University ECE 546 Fall 2011 N F f
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Delay Formula for an Inverter elay   ~ C C R Delay L int S     / 1 / 1 69 . 0 0
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ece546fall11_09 - ECE ECE 546 - VLSI Systems Design Lecture...

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