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ece546fall11_11

# ece546fall11_11 - ECE ECE 546 VLSI Systems Design Lecture...

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ECE 546 ECE 546 - VLSI Systems Design VLSI Systems Design ecture ecture 1: Dynamic Logic 1: Dynamic Logic Lecture Lecture 11: Dynamic Logic 11: Dynamic Logic Fall Fall 2011 2011 W. Rhett Davis NC State University ith significant material from ith significant material from abaey abaey handrakasan handrakasan and and ikoli ć Slide 1 © W. Rhett Davis NC State University ECE 546 Fall 2011 with significant material from with significant material from Rabaey Rabaey, , Chandrakasan Chandrakasan, and , and Nikoli Nikoli

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Announcements Homework #5 due Tuesday Midterm Review in 1 week o office hours that day » No office hours that day » Special Office Hours 1-3pm Wednesday idterm Exam in 12 days Midterm Exam in 12 days Slide 2 © W. Rhett Davis NC State University ECE 546 Fall 2011
Summary of Last Lecture How do you find the static power for a ratioed gic gate? logic gate? What is the output voltage swing of a pass- transistor gate? a cascaded gate? How do you compute the delay through a pass- ansistor gate? transistor gate? Slide 3 © W. Rhett Davis NC State University ECE 546 Fall 2011

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Today’s Lecture rinciples of Dynamic Logic Principles of Dynamic Logic (6.3.1) Dynamic Logic Signal Integrity Issues (6.3.3) Slide 4 © W. Rhett Davis NC State University ECE 546 Fall 2011
Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to GND or V DD via a low resistance path. omplementary CMOS: » Complementary CMOS: fan-in of n requires 2 n ( n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high pedance nodes impedance nodes. » requires on n + 2 ( n +1 N-type + 1 P-type) transistors Slide 5 © W. Rhett Davis NC State University ECE 546 Fall 2011

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Dynamic Gate M p Clk Out Out Clk M p In 1 In 2 PDN In C L A C 3 M e Clk Clk B M e Two phase operation Precharge (Clk = 0) Slide 6 © W. Rhett Davis NC State University ECE 546 Fall 2011
Dynamic Gate M p Clk Out Out Clk M p In 1 In 2 PDN In C L A C 3 M e Clk Clk B M e Two phase operation Evaluate (Clk = 1) Slide 7 © W. Rhett Davis NC State University ECE 546 Fall 2011

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Conditions on Output
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ece546fall11_11 - ECE ECE 546 VLSI Systems Design Lecture...

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