ece546fall11_12

ece546fall11_12 - ECE ECE 546 - VLSI Systems Design Lecture...

Info iconThis preview shows pages 1–8. Sign up to view the full content.

View Full Document Right Arrow Icon
ECE 546 ECE 546 - VLSI Systems Design VLSI Systems Design ecture 12: ynamic Logic Lecture 12: Lecture 12: Dynamic Logic, Dynamic Logic, Latches & Flip Latches & Flip-Flops Flops Fall Fall 2011 2011 W. Rhett Davis NC State University ith significant material from ith significant material from abaey abaey handrakasan handrakasan and and ikoli ć Slide 1 © W. Rhett Davis NC State University ECE 546 Fall 2011 with significant material from with significant material from Rabaey Rabaey, , Chandrakasan Chandrakasan, and , and Nikoli Nikoli
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Announcements HW#5 Due Today Midterm Review Thursday Midterm Exam in 1 week HW#6 Due in 3 weeks Slide 2 © W. Rhett Davis NC State University ECE 546 Fall 2011
Background image of page 2
Summary of Last Lecture What are V M , V IL , and V IH for a dynamic gate? Under what conditions do you need to determine the amount of charge-sharing for a dynamic gate? How can you tell whether a gate is susceptible to partial or complete charge sharing? hat signal tegrity issues other than charge haring What signal-integrity issues other than charge-sharing threaten the correct functionality of a dynamic gate? Slide 3 © W. Rhett Davis NC State University ECE 546 Fall 2011
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Today’s Lecture ascading Dynamic Gates (6 3 4) Cascading Dynamic Gates (6.3.4) Power Consumption of Dynamic Logic (6.3.2) Principles of Sequential Logic (7.1) Slide 4 © W. Rhett Davis NC State University ECE 546 Fall 2011
Background image of page 4
Cascading Dynamic Gates V Clk Out1 M p M p Clk Out2 Clk Clk In M M Clk In ut1 V Tn e e Out1 Out2 V t nly 0 transitions allowed at inputs! Slide 5 © W. Rhett Davis NC State University ECE 546 Fall 2011 Only 0 1 transitions allowed at inputs!
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Domino Logic M p Clk Out1 M p Clk Out2 M kp In 1 DN In PDN 1 1 1 0 0 0 0 1 In 2 PDN In 3 M Clk 4 In 5 M e Clk Slide 6 © W. Rhett Davis NC State University ECE 546 Fall 2011
Background image of page 6
Why Domino?
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 8
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 29

ece546fall11_12 - ECE ECE 546 - VLSI Systems Design Lecture...

This preview shows document pages 1 - 8. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online