ece546fall11_14

ece546fall11_14 - ECE ECE 546 - VLSI Systems Design Lecture...

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ECE 546 ECE 546 - VLSI Systems Design VLSI Systems Design ecture ecture 4: Dynamic Latches 4: Lecture Lecture 14: Dynamic Latches, 14: Flip Flip-Flops, & Pipelining Flops, & Pipelining Fall Fall 2011 2011 W. Rhett Davis NC State University ith significant material from ith significant material from abaey abaey handrakasan handrakasan and and ikoli ć Slide 1 © W. Rhett Davis NC State University ECE 546 Fall 2011 with significant material from with significant material from Rabaey Rabaey, , Chandrakasan Chandrakasan, and , and Nikoli Nikoli
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Announcements HW#6 Due Tuesday Start forming project groups » 3-person groups » e-mail me your names and Unity IDs » I will assign you a group number and post it to the class web- age page Slide 2 © W. Rhett Davis NC State University ECE 546 Fall 2011
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Summary of Last Lecture Is this a positive or a negative latch? Does is CLK work by loop-breaking or loop-forcing? How should you size the transistors? D CLK Q How do you calculate the minimum clock-period for a design? What are the types of timing constraints? Which one is the most critical to satisfy? Using the skew definition from the last lecture, if the clock edge at the source register arrives BEFORE the Slide 3 © W. Rhett Davis NC State University ECE 546 Fall 2011 clock edge at the destination register, is the skew positive or negative?
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Today’s Lecture ynamic Latches & Registers (7 3) Dynamic Latches & Registers (7.3) Pipelining (7.5) Slide 4 © W. Rhett Davis NC State University ECE 546 Fall 2011
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Static vs. Dynamic Latches Dynamic (charge-based) Static D CLK Q CLK CLK CLK Q CLK D Slide 5 © W. Rhett Davis NC State University ECE 546 Fall 2011
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Dynamic Flip-Flop 1 2 1 2 What are the dynamic nodes? Rising-Edge or Falling Edge Triggered? Estimate t su , t hold , and t c-q based on the delays of the transmission gates and inverters. Slide 6 © W. Rhett Davis NC State University ECE 546 Fall 2011
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Clock-Overlap Problem: Both latches are ansparent transparent Assume t su and t hold are relative to CLK What timing constraints are needed to ensure proper peration? operation?
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This note was uploaded on 01/26/2012 for the course EE 546 taught by Professor Whett during the Spring '11 term at N.C. State.

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ece546fall11_14 - ECE ECE 546 - VLSI Systems Design Lecture...

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