ece546fall11_18

ece546fall11_18 - ECE ECE 546 - VLSI Systems Design Lecture...

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ECE 546 ECE 546 - VLSI Systems Design VLSI Systems Design ecture ecture 8: 8: Lecture Lecture 18: 18: Project Introduction Fall Fall 2011 2011 W. Rhett Davis NC State University ith significant material from ith significant material from abaey abaey handrakasan handrakasan and and ikoli ć Slide 1 © W. Rhett Davis NC State University ECE 546 Fall 2011 with significant material from with significant material from Rabaey Rabaey, , Chandrakasan Chandrakasan, and , and Nikoli Nikoli
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Announcements HW #8 Due in 1 Week Project Milestone #1 Due in 1 Week Slide 2 © W. Rhett Davis NC State University ECE 546 Fall 2011
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Today’s Lecture roject troduction Project Introduction » Specification equirements » Requirements » Milestones rading » Grading » Project Groups Slide 3 © W. Rhett Davis NC State University ECE 546 Fall 2011
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4-Stage Router Pipeline Critical Component in On-Chip Interconnects » e.g. ARM/AMBA AXI Buses, On-chip routers for Networks-on-Chip IFO stores inputs (stage 1) FIFO stores inputs (stage 1) Acceptable Routes Evaluated to a set of requests (stage 2) rbiter decides which input gets which output (stage 3) Slide 4 © W. Rhett Davis NC State University ECE 546 Fall 2011 Arbiter decides which input gets which output (stage 3) Crossbar connects selected inputs to their outputs (stage 4)
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Project Specification 3x3x3 Router cludes last two stages of pipeline only Slide 5 © W. Rhett Davis NC State University ECE 546 Fall 2011 Includes last two stages of pipeline only Omits pipeline register between stages
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Arbitration Cell Arbitration is typically ccomplished with an array RTO RTI OVI accomplished with an array Arbitration Cell » One cell for each in-out pair GR OVO RQ WAIT » RQ raised if input wants output » WAIT raised if output busy » RT signal indicates that this input TI OVI s g a d cates t at t s put has already been routed (lower num. outputs preferred) » OV signal indicates that this output is RTO RTI gp overridden by lower numbered input » GR signal indicates this output granted to this input GR RQ WAIT Slide 6 © W. Rhett Davis NC State University ECE 546 Fall 2011 (NOTE: each output should have at most 1 input granted) OVO
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Complete Arbiter OVI OVI OVI WAIT_o0 WAIT_o1 WAIT_o2 RTO GR OVO RQ WAIT RTI RTO GR OVO RQ WAIT RTI RTO GR OVO RQ WAIT RTI RQ i0 o0 GR i0 o0
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ece546fall11_18 - ECE ECE 546 - VLSI Systems Design Lecture...

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