ece546fall11_21

ece546fall11_21 - ECE ECE 546 - VLSI Systems Design Lecture...

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ECE 546 ECE 546 - VLSI Systems Design VLSI Systems Design ecture ecture 1: Clock Trees Heat 1: Clock Trees Heat Lecture Lecture 21: Clock Trees, Heat 21: Clock Trees, Heat Fall Fall 2011 2011 W. Rhett Davis NC State University ith significant material from ith significant material from abaey abaey handrakasan handrakasan and and ikoli ć Slide 1 © W. Rhett Davis NC State University ECE 546 Fall 2011 with significant material from with significant material from Rabaey Rabaey, , Chandrakasan Chandrakasan, and , and Nikoli Nikoli
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Announcements roject ilestone #2 uein1week Project Milestone #2 Due in 1 week Slide 2 © W. Rhett Davis NC State University ECE 546 Fall 2011
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Summary of Last Lecture ow do the delay and area of a carry- How do the delay and area of a carry lookahead adder vary with the number of bits? When is it useful to use a carry-save adder? How does a carry-save multiplier differ from an array multiplier? yp Slide 3 © W. Rhett Davis NC State University ECE 546 Fall 2011
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Today’s Lecture ayout Tips Layout Tips Clock Trees Heat Slide 4 © W. Rhett Davis NC State University ECE 546 Fall 2011
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Avoid Jogs Best to align source and destination to duce area needed for wiring reduce area needed for wiring If jogs are necessary, it’s generally better to restrict wires to alternating directions » M1 horizontal, M2 vertical, M3, horizontal, etc. » Reduces the number of metal layers required robably won’t affect your project Slide 5 © W. Rhett Davis NC State University ECE 546 Fall 2011 » Probably won t affect your project
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Share Power Rails and Wells Always share wells and power rails when stacking cells vertically Also try putting well- contact directly on the rail to save area (one well contact for two cells) Slide 6 © W. Rhett Davis NC State University ECE 546 Fall 2011
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Today’s Lecture ayout Tips Layout Tips Clock Trees Heat Slide 7 © W. Rhett Davis NC State University ECE 546 Fall 2011
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Where we left off … Skew and insertion-delay can be defined for a pair of registers. When referring to a clock-tree, the definition is slightly different kew =t s(max) - s(min) s = t s(min) +t kew t skew t ins(max) t ins(min) t ins t ins(min) t skew /2 Slide 8 © W. Rhett Davis NC State University ECE 546 Fall 2011
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The Clock-Tree Design Problem . . . How to get a signal from the clock source to the Slide 9 © W. Rhett Davis NC State University ECE 546 Fall 2011 clock sinks?
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The Simplest Approach . . . Progressively sized buffer chain to drive the large load roblem: Large skew due to different RC wire delays Slide 10 © W. Rhett Davis NC State University ECE 546 Fall 2011 Problem: Large skew due to different RC wire delays
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A Better Approach . . . Clock-Tree allows equalizing wire-delays between branches Shown here: Binary Clock Tree » Fan-out of 2 for each branch Slide 11 © W. Rhett Davis NC State University ECE 546 Fall 2011 » Typically the highest power, lowest skew
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Ideal Binary Clock Tree H-Tree Equalizes wire- lengths to all loads Problem: Clock- sinks are typically not evenly distributed CLOCK Slide 12 © W. Rhett Davis NC State University ECE 546 Fall 2011
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