Exam 2 review

Exam 2 review - Victim Blocks and Replacement Policies...

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Exam II Review Chapter 4 CPUs Components and their roles Clock Rate Decoders (section 4.13) Buses Architectures Components Control Protocols & Arbitration Byte vs Word Addressing Memory interleaving Interrupts (maskable vs non-maskable) Interrupt processing Chapter 5 Instruction Sets Fixed vs variable length instructions Big endian vs. little endian Instruction Addressing Modes Immediate Direct Indirect Indexed Pipelining (ILP vs PLP) Chapter 6 Types of Memory RAM vs ROM SRAM vs DRAM DDR types Memory Hierarchy Hit vs Miss (Hit Rate vs Miss Rate) Localities Cache Mapping (content addressable memory) Direct Mapped Fully-Associative Mapped Set-Associative Mapped
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Unformatted text preview: Victim Blocks and Replacement Policies Dirty Blocks and Write Policies Cache Levels & types (data vs instruction) Virtual memory • Paging • Segmentation • Virtual vs physical address • Fragmentation (internal vs external) • Page faults Chapter 7 Amdahl’s law I/O control methods • Programmed • Interrupt-Driven • DMA • Channel Block vs Character I/O Synchronous vs Asynchronous Serial vs Parallel Media (Hard Disks) • Tracks and sectors • Blocks • Read/write head • Areal density • Seek time, rotational delay, etc. • Controller and armature Optical media • CD vs DVD vs Blue Laser media • Constant linear velocity Tape…it’s slow! RAID • Mirror, Striping, Parity • Levels...
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This note was uploaded on 01/30/2012 for the course CNIT 176 taught by Professor Hansen during the Fall '09 term at Purdue.

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