Lecture 4 - CNIT 17600 IT Architectures CPU Architectures...

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CNIT 17600 IT Architectures CPU Architectures and Instruction Sets
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Objectives 2 Understand the factors involved in instruction set architecture design Gain familiarity with memory addressing modes Understand the concepts of instruction-level pipelining and its affect upon execution performance
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5.1 Introduction 3 We present a detailed look at different instruction formats, operand types, and memory access methods We will see the interrelation between machine organization and instruction formats This leads to a deeper understanding of computer architecture in general
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5.2 Instruction Formats 4 Instruction sets are differentiated by the following: Number of bits per instruction Stack-based or register-based Number of explicit operands per instruction Operand location Types of operations Type and size of operands
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Instructions Instruction Lowest-level command A bit string, logically divided into components operation code(s) and operand(s) Template describing Op code position and length Operand position, type, and length Vary among architectures op code size, meaning of specific op code values, data types used as operands, length and coding format of each type of operand 5
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Op Code and Operands Op Code Unique binary number for an instruction Operands Input values for the instruction 6
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5.2 Instruction Formats 7 Instruction set architectures are measured according to: Main memory space occupied by a program Instruction complexity Instruction length (in bits) Total number of instructions in the instruction set
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5.2 Instruction Formats 8 In designing an instruction set, consideration is given to: Instruction length Whether short, long, or variable Number of operands Number of addressable registers Memory organization Whether byte- or word addressable Addressing modes Choose any or all: direct, indirect or indexed
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5.2 Instruction Formats 9 Byte ordering, or endianness , is another major architectural consideration If we have a two-byte integer, the integer may be stored so that the least significant byte is followed by the most significant byte or vice versa In little endian machines, the least significant byte is followed by the most significant byte Big endian machines store the most significant byte first (at the lower address)
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5.2 Instruction Formats 10 As an example, suppose we have the number 0x12345678
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5.2 Instruction Formats 11 Big endian: Is more natural for human readability The sign of the number can be determined by looking at the byte at address offset 0 Strings and integers are stored in the same order Little endian: Makes it easier to place values on non-word boundaries Conversion from a 16-bit integer address to a 32-bit integer address does not require any arithmetic
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5.2 Instruction Formats 12 The next consideration for architecture design concerns how the CPU stores data We have three choices: 1. A stack architecture
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This note was uploaded on 01/30/2012 for the course CNIT 176 taught by Professor Hansen during the Fall '09 term at Purdue University-West Lafayette.

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Lecture 4 - CNIT 17600 IT Architectures CPU Architectures...

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