EE 330 Exam 3 Spring 2011(1)

EE 330 Exam 3 Spring 2011(1) - EE 330 Exam 3 Spring 2011...

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Page 1 of 11 EE 330 Name_ _ _ _ _ _ _ _ _ _ _ _ _ _ Exam 3 Spring 2011 Instructions: This is a 50 minute exam. Students may bring 3 page of notes (front and back) to this exam. The points for the first eight questions are as indicated. The 5 problems are worth 16 points each. Please solve problems in the space provided on this exam and attach extra sheets only if you run out of space in solving a specific problem. If references semiconductor processes are needed beyond what is given in a specific problem or question, assume a CMOS process is available with the following key process parameters; n C OX =100 A/v 2  p C OX = n C OX /3 ,V TNO =0.5V, V TPO = - 0.5V, C OX =2fF/ 2 , = 0, and    If reference to a bipolar process is made, assume this process has key process parameters J S =10 -15 A/ 2 , β=100 and V AF = ∞. If any other process parameters are needed, use the process parameters associated with the process described on the attachments to this exam. Specify clearly what process parameters you are using in any solution requiring process parameters. Also attached to this exam is a table discussed in class that relates to the basic amplifier configurations. 1. (2pts) What is the major reason that CMOS technology has replaced NMOS or PMOS technology for manufacturing logic circuits? 2. (2pts) When building logic circuits with CMOS NAND and NOR gates, any logic function can be implemented with only NAND gates, with only NOR gates, or with a combination of NAND and NOR gates. There is often an advantage for using only NAND gates. What is this advantage? 3. (3pts)
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EE 330 Exam 3 Spring 2011(1) - EE 330 Exam 3 Spring 2011...

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