EE 330 HW 1 Solutions Spring 2012

EE 330 HW 1 Solutions Spring 2012 - HW1 Problem 1 Assume a...

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HW1 Problem 1 Assume a simple circuit requires 10,000 MOS transistors on a die and that all transistors are minimum sized. If the transistors are fabricated in a 32nm CMOS process and the spacing overhead for the transistors is a factor of 10, determine the number of die that can be fabricated on an 12” silicon wafer. Neglect the area required for the bonding pads of the circuit. Solution 10 2 32 32 10 10000 1.024 10 die A nm nm m 22 (6 ) 0.07296 wafer A in m 8 7.12 10 wafer die die A n A Problem 2 If the cost of a 12 inch wafer is $6000, what is the cost/die for the circuit in Problem 1. Solution 6 cos / $8.42 10 wafer die C t die n Problem 3 How many 20 nm transistors could be placed on a die that has the same area as the cross-section of a human hair? Assume a 10x spacing overhead. Solution 10 ~ 200 hair d um um 2 2 20000 ~ 8000000 10 (20 ) hair hair die die Ar n A nm
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Problem 4 The clock frequency of microprocessors has not increased appreciably for the past several years yet performance is improving through the parallelism offered by multiple cores. Why is it more energy efficient to use multiple cores on a die each operating at a lower clock rate than to have a single core operating at a higher clock frequency? Solution 1) As a consequence of lower-power design requirements, system architects have been forced to innovate using multiple processor cores typically running parallel threads at lower frequencies. This enables processors to turn off when not actively doing computations.
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EE 330 HW 1 Solutions Spring 2012 - HW1 Problem 1 Assume a...

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