EE 330 Lab 3 Fall 2011

EE 330 Lab 3 Fall 2011 - EE 330 Laboratory 3 Layout and LVS...

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Page 1 of 6 Update Date:9/5/2011 EE 330 Laboratory 3 Layout and LVS (Layout Versus Schematic) Fall 2011 Objective: The objective of this experiment is introduce the concept of layout of circuits. In this context, design rules and CAD tools used for verifying that all design rules are satisfied, termed design rule checkers (DRC), will be introduced. A final objective will be to verify that the actual equivalent circuit corresponding to the layout agrees with the original circuit schematic. A CAD tool that performs this latter function, termed a layout versus schematic (LVS) tool will be used for this purpose. Note: If your inverter is still sized at 45 and 15 microns for PMOS and NMOS, respectively, re-size it back down to 4.5 and 1.5 microns. Part 1 Layout view In our design environment, a layout view gives a representation of how the semiconductor circuit will look like once fabricated. Once the layout is complete, is found to be free of any design rules violations, and is electrically equivalent to the schematic, it can be sent to the foundry for fabrication. We will create the layout of the inverter we created in the previous lab. Create a layout view of the inverter cell in lablib library. The Virtuoso layout editor window will open. You will notice that on the left is a toolbox titled Layers . It lists all the available layers in the process that is used, along with their corresponding color code. Since we attached the library to AMI06, our lambda is 0.3u.
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Page 2 of 6 Update Date:9/5/2011 In the layout editor window, notice how the mouse snaps to the closest coordinate unit. To check your grid settings, go to Options Display Grid Controls . It is suggested that the and the minor and major spacing be at 1 and 5 respectively . Based on the lecture notes, draw a layout of your inverter. Make sure you draw the transistor sizes according to the sizes you have in the schematic. Show this drawing to the TA. The shapes we are able to draw are all rectangular. For example, to draw a
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EE 330 Lab 3 Fall 2011 - EE 330 Laboratory 3 Layout and LVS...

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