EE 330 Lab 4 Spring 2011

EE 330 Lab 4 Spring 2011 - EE 330 Laboratory 4 From Boolean...

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Page 1 of 4 Updated on 1/26/2011 EE 330 Laboratory 4 From Boolean equation to Silicon Fall 2010 Objective: The objective of this experiment is to implement a Boolean function description in silicon, given area and pin constraints. A second object is to introduce the concept of parameterized cells (pcells) which are useful for making layouts of widely-used circuits when the basic circuit structure remains fixed but when some characteristics of the circuit, such as the device dimensions or the number of elements in the circuit, may change. Introduction A simplified Custom IC design flow is shown in the flow chart. From the flow chart, we can observe that we now have the basic skills to do a complete design of a simple circuit. In this experiment, we will take the system description in the form of a simple Boolean expression and convert it to a layout for fabrication through MOSIS. Before we start the design, a layout technique that can save considerable time on the part of the designer will be introduced. Part 1: Layout of an inverter using pcells: From the previous experiment that focused on layout basics, most likely concluded that it takes considerable time to layout even a simple circuit (e.g. a Boolean inverter) and considerable attention must be devoted throughout the layout process to avoid creating either layout errors or even circuit errors. One way to expedite the layout process is to use parameterized cells (pcells). Pcells are “macros” that take have numeric arguments as an input and that generate as an output a layout that is “correct by construction”. For example, we will consider as an example a pcell where the length and the width of a transistor serve as numeric input parameters to create the layout of an NMOS transistor (exclusive of a bulk connection!). The available pcells that are available
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EE 330 Lab 4 Spring 2011 - EE 330 Laboratory 4 From Boolean...

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