EE 330 Lab 11 Fall 2010

EE 330 Lab 11 Fall 2010 - EE 330 Laboratory Experiment...

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EE 330 Laboratory Experiment Number 11 Design, Simulation and Layout of Digital Circuits using Hardware Description Languages Purpose: The purpose of this experiment is to develop methods for using Hardware Description Languages for the design of digital circuits. Part 1: Background Hardware Description Languages (HDL) are widely used for representing digital systems at both the Behavioral and Structural levels. Full functionality of a digital system can ideally be captured in a HDL and the design of digital circuits is often accomplished within the confines of an HDL framework. At the appropriate level in the HDL, CAD tools can take a design down to the mask level for fabrication in silicon with minimal engineering intervention at the Physical Level in the design process. A system appropriately represented in a HDL can be simulated to predict not only the functionality of sequential and combinational logic circuits, but also timing information about how those circuits are predicted to perform when instantiated in silicon. The two most widely used HDLs today are Verilog and VHDL. There is considerable similarity between these two languagees and engineers are expected to be proficient in both. In this laboratory experiment we will limit our discussion to Verilog which has become more popular in US industry today. Specifically we will focus on how a HDL can be used for design and simulation of digital integrated circuits. Appendix A of the Weste and Harris text has a brief discussion of Verilog and students should become familiar with the material in this appendix. There are also numerous books and WEB sites devoted to a discussion of Verilog. Beyond the basic introduction to Verilog discussed in this laboratory experiment, students will be expected to take the initiative to develop their own HDL skills to the level needed to support the digital design component of this course. Part 1.1: Structure of Verilog Representations A Verilog representation of a digital system, be it a small or a very large system, is characterized by a set of modules that describe the system. A large system will be comprised of a large number of nested modules whereas a small system may be comprised of only a single module. As such, the main building block in Verilog is the module . The structure of a module includes statements about input/output variable mappings along with a description about how the input and output variables are related. An example of a module named “testcircuit” is shown below
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module testcircuit (vout, vdd, vss, vin); output vout; inout vdd; inout vss; input vin; assign vout = ~vin; endmodule This module has one output, vout, one input, vin, and two bidirectional ports, vdd and vss. The relationship between the input and output for this simple module is defined by the assign statement. The module description is always terminated with an endmodule statement. In Cadence, we can create behavioral modules several ways, two of which will be discussed in this experiment. Symbol-Based Module Creation
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EE 330 Lab 11 Fall 2010 - EE 330 Laboratory Experiment...

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