EE 330 Lect 1 Spring 2011

EE 330 Lect 1 Spring 2011 - EE 330 Fall 2009 Integrated...

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EE 330 Fall 2009 Lecture Instructor: Randy Geiger 2133 Coover rlgeiger@iastate.edu 294-7745 Lab Instructors: Sheng-Huang (Alex) Lee and Dan Congreve Web Site: http://class.ece.iastate.edu/ee330/ Lecture: MWF 9:00 1012 Coover Lab: Sec A Tues 8:00 - 10:50 2046 Coover Sec B Thur 8:00 – 10:50 2046 Coover Sec C Thur 3:10 – 6:00 2046 Coover Integrated Electronics
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Catalog Description E E 330. Integrated Electronics. (Same as Cpr E 330.) (3-3) Cr. 4. F.S. Prereq: 201, credit or enrollment in 230, Cpr E 210. Semiconductor technology for integrated circuits. Modeling of integrated devices including diodes, BJTs, and MOSFETs. Physical layout. Circuit simulation. Digital building blocks and digital circuit synthesis. Analysis and design of analog building blocks. Laboratory exercises and design projects with CAD tools and standard cells.
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Topical Coverage • Semiconductor Processes • Device Models (Diode,MOSFET,BJT, Thyristor) • Layout • Simulation and Verification • Basic Digital Building Blocks • Behavioral Design and Synthesis – Standard cells • Basic Analog Building Blocks
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Topical Coverage Weighting Logic Circuits Fabrication Technology Diodes MOS Devices Bipolar Devices Small Signal Analysis and Models Linear MOSFET and BJT Applications 7.5 3.5 6 2.5 8 7 6.5 (BJTs and Thyristors)
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Textbook: CMOS VLSI Design – A Circuits and Systems Perspective by Weste and Harris Addison Wesley/Pearson, 2011 - Fourth edition
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Grading Policy 3 Exams 100 pts each 1 Final 100 pts. Homework 100 pts.total Quizzes/Attendance 100 pts Lab and Lab Reports 100 pts.total Design Project (tentative) 100 pts.
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Attendance and Equal Access Policy Participation in all class functions and provisions for special circumstances will be in accord with ISU policy Attendance of any classes or laboratories, turning in of homework, or taking any exams or quizzes is optional however grades will be assigned in accord with described grading policy. No credit will be given for any components of the course without valid excuse if students choose to not be present or not to contribute. Successful demonstration of ALL laboratory milestones and submission of complete laboratory reports for ALL laboratory experiments to TA by deadline established by laboratory instructor is, however, required to pass this course.
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Instructor Access: • Office Hours – Open-door policy – MWF 10:00-11:00 reserved for EE 330 students – By appointment • Email rlgeiger@iastate.edu – Include EE 330 in subject
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Teaching Assistant Access: Dan Cosgreve – congreve.dan@gmail.com – Room xxxx Coover Alex Lee -alexlsh@iastate.edu - Room xxxx Coover
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• Course Web Site: http://class.ece.iastate.edu/ee330
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Fundamentals of Microelectronics by B. Razavi, Wiley, 2008 CMOS Circuit Design, Layout, and Simulation (3rd Edition) by Jacob Baker, Wiley-IEEE Press, 2010. The Art of Analog Layout
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This document was uploaded on 01/31/2012.

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EE 330 Lect 1 Spring 2011 - EE 330 Fall 2009 Integrated...

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