EE 330 Lect 3 Fall 2011

EE 330 Lect 3 Fall - EE 330 Lecture 3 Basic Concepts Historical Background Feature Sizes and Yield Review from Last Time Sophisticated Integrated

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EE 330 Lecture 3 Basic Concepts Historical Background, Feature Sizes and Yield
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Review from Last Time Sophisticated Integrated CAD Toolsets are extensively used in the industry to design integrated circuits Minimize the chances of an error Real asset to (and not a competitor of) the engineer Critical to pay attention to what tools tell you Feature size good metric for characterizing capabilities of a process State of the art at about 65nm Pitch sometimes used instead of feature size Drawn and actual features may differ Bragging rights focus on actual rather than drawn features Yield often determined by statistically independent events Cost of Wafers in $800 to $3000 range depending on size and process n P Y 2 / 5 . 2 $ cm C area unit per
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MOS Transistor Gate Source Drain W L Actual Drain and Source at Edges of Channel Review from Last Time
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MOS Transistor Gate Source Drain W eff L eff Effective Width and Length Generally Smaller than Drawn Width and Length Review from Last Time
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Size of Atoms and Molecules in Semiconductor Processes o A 7 . 2 o A 4 . 5 o A 5 . 3 Silicon: Average Atom Spacing Lattice Constant S i O 2 Average Atom Spacing Breakdown Voltage 20KV/cm Air 0 A 10mV/ to 5 10MV/cm 5 Physical size of atoms and molecules place fundamental limit on conventional scaling approaches Review from Last Time
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Defects in a Wafer Defect Dust particles and other undesirable processes cause defects Defects in manufacturing cause yield loss
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Yield Issues and Models Defects in processing cause yield loss The probability of a defect causing a circuit failure increases with die area The circuit failures associated with these defects are termed Hard Faults This is the major factor limiting the size of die in integrated circuits Wafer scale integration has been a ―gleam in the eye‖ of designers for 3 decades but the defect problem continues to limit the viability of such approaches Several different models have been proposed to model the hard faults
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Yield Issues and Models • Parametric variations in a process can also cause circuit failure or cause circuits to not meet desired performance specifications (this is of particular concern in analog and mixed-signal circuits) • The circuits failures associated with these parametric variations are termed Soft Faults • Increases in area, judicious layout and routing, and clever circuit design techniques can reduce the effects of soft faults
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Hard Fault Model Ad H e Y Y H is the probability that the die does not have a hard fault A is the die area d is the defect density (typically 1cm -2 < d < 2cm -2 ) Industry often closely guards the value of d for their process Other models, which may be better, have the same general functional form
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Soft Fault Model Soft fault models often dependent upon design and application k A ρ σ Often the standard deviation of a parameter is dependent upon the reciprocal of the square root of the parameter sensitive area ρ is a constant dependent upon the architecture and the process A k is the area of the parameter sensitive area
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EE 330 Lect 3 Fall - EE 330 Lecture 3 Basic Concepts Historical Background Feature Sizes and Yield Review from Last Time Sophisticated Integrated

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