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EE 330 Lect 3 Fall 2011

EE 330 Lect 3 Fall 2011 - EE 330 Lecture 3 Basic Concepts...

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EE 330 Lecture 3 Basic Concepts Historical Background, Feature Sizes and Yield
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Review from Last Time Sophisticated Integrated CAD Toolsets are extensively used in the industry to design integrated circuits Minimize the chances of an error Real asset to (and not a competitor of) the engineer Critical to pay attention to what tools tell you Feature size good metric for characterizing capabilities of a process State of the art at about 65nm Pitch sometimes used instead of feature size Drawn and actual features may differ Bragging rights focus on actual rather than drawn features Yield often determined by statistically independent events Cost of Wafers in $800 to $3000 range depending on size and process n P Y 2 / 5 . 2 $ cm C area unit per
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MOS Transistor Gate Source Drain W L Actual Drain and Source at Edges of Channel Review from Last Time
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MOS Transistor Gate Source Drain W eff L eff Effective Width and Length Generally Smaller than Drawn Width and Length Review from Last Time
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