EE 330 Lect 6 Fall 2011

EE 330 Lect 6 Fall 2011 - EE 330 Lecture 6 Improved Device...

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EE 330 Lecture 6 Improved Device Models Stick Diagrams Technology Files
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MOS Transistor Qualitative Discussion of n-channel Operation Gate Drain Source Bulk n-channel MOSFET Drain Gate Source D S G = 0 D S G = 1 Equivalent Circuit for n-channel MOSFET This is the first model we have for the n-channel MOSFET ! Source assumed connected to ground Review from Last Time
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MOS Transistor Qualitative Discussion of p-channel Operation Gate Drain Source Bulk p-channel MOSFET Drain Gate Source Equivalent Circuit for p-channel MOSFET D S G = 1 D S G = 0 This is the first model we have for the p-channel MOSFET ! Source assumed connected to V DD and Boolean G at gate is relative to ground Review from Last Time
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MOS Transistor Comparison of Operation Drain Gate Source Drain Gate Source D S G = 1 D S G = 0 D S G = 0 D S G = 1 Review from Last Time
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Pull-up and Pull-down Networks 1. PU network comprised of p-channel devices 2. PD network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time V DD X Y PUN PDN n 1. V H =V DD , V L =0 (too good to be true?) 2. P H =P L =0 (too good to be true?) 3. t HL =t LH =0 (too good to be true?) These 3 properties are inherent in Boolean circuits with these 3 characteristics Three key characteristics of Static CMOS Gates Three properties of Static CMOS Gates (based upon simple switch-level model) Review from Last Time
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Example 3: XOR Function A B Y Y=A B Y=AB + AB A Y B A widely-used 2-input Gate Static CMOS implementation 22 transistors 5 levels of logic Delays unacceptable and device count is too large ! Review from Last Time
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Complex Gates V DD X Y PUN PDN n Nomenclature: When the logic gate shown is not a multiple-input NAND or NOR gate but has Characteristics 1, 2, and 3 above, the gate will be referred to as a Complex Logic Gate Complex Logic Gates also implement static logic functions and some authors would refer to this as Static CMOS Logic as well but we will make the distinction and refer to this as “Complex Logic Gates” Review from Last Time
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Complex Gates V DD X Y PUN PDN n 1. Implement in the PDN 2. Implement Y in the PUN (must complement the input variables since p- channel devices are used) Y Complex Gate Design Strategy: (Y and expressed as either SOP or POS form) Y
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XOR in Complex Logic Gates A B Y Y=A B Need Y and Y in standard SOP or POS form
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XOR in Complex Logic Gates A B Y Y=A B Y=AB + AB   Y= AB + AB Y=AB AB     Y= A+B • A+B
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XOR in Complex Logic Gates A B Y     Y= A+B • A+B Y=AB + AB PDN PUN A B A B A A B B
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XOR in Complex Logic Gates A B Y     Y= A+B • A+B Y=AB + AB A A B B 12 transistors and 2 levels of logic Notice a significant reduction in the number of transistors required A A B B A B A B Y V DD
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XOR in Complex Logic Gates A B Y     Y= A+B • A+B Y=AB + AB Multiple PU and PD networks can be used                 Y= A+B • A+B A• A+B + B• A+B A•B + A•B A A B B A A B B
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This document was uploaded on 01/31/2012.

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EE 330 Lect 6 Fall 2011 - EE 330 Lecture 6 Improved Device...

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