{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

EE 330 Lect 6 Spring 2011

# EE 330 Lect 6 Spring 2011 - EE 330 Lecture 6 Improved...

This preview shows pages 1–12. Sign up to view the full content.

EE 330 Lecture 6 Improved Device Models Stick Diagrams Technology Files

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Quiz 5 Design, using the Complex Logic Gates approach, a logic circuit that implements the Boolean function Assume the input variables available are A, B, and C. How many transistors are required for this implementation and how many levels of logic are there? Y=AB+C
And the number is …. 6 3 1 2 4 5 7 8 9

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
And the number is …. 6 3 1 2 4 5 7 8 9 2
Quiz 5 Design, using the Complex Logic Gates approach, a logic circuit that implements the Boolean function Assume the input variables available are A, B, and C. How many transistors are required for this implementation and how many levels of logic are there? Y=AB+C Solution: Implement PU network with Y Implement PD network with Y     Y=AB+C = AB C = A+B •C B C A B A C PDN PUN

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Quiz 5 Design, using the Complex Logic Gates approach, a logic circuit that implements the Boolean function Assume the input variables available are A, B, and C. How many transistors are required for this implementation and how many levels of logic are there? Y=AB+C B C A B A C Y V DD GND A A C C 10 transistors 2 levels of logic
Pull-up and Pull-down Networks 1. PU network comprised of p-channel devices 2. PD network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time V DD X Y PUN PDN n 1. V H =V DD , V L =0 (too good to be true?) 2. P H =P L =0 (too good to be true?) 3. t HL =t LH =0 (too good to be true?) These 3 properties are inherent in Boolean circuits with these 3 characteristics Three key characteristics of Static CMOS Gates Three properties of Static CMOS Gates (based upon simple switch-level model) Review from Last Time

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Complex Gates V DD X Y PUN PDN n 1. Implement in the PDN 2. Implement Y in the PUN (must complement the input variables since p- channel devices are used) Y Complex Gate Design Strategy: Review from Last Time
XOR in Complex Logic Gates A B Y     Y= A+B • A+B Y=AB + AB Multiple PU and PD networks can be used                 Y= A+B • A+B A• A+B + B• A+B A•B + A•B A A B B A A B B Review from Last Time

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Pass Transistor Logic Y A B  A B Y R A B 2 transistors, 1 resistor, one level of logic A B Y R A B Y A B Review from Last Time
Pass Transistor Logic B A Y Requires only 1 transistor (and a resistor) - Pass transistor logic can offer significant reductions in complexity for some functions (particularly noninverting) - Resistor may require more area than several hundred or even several thousand transistors - Signal levels may not go to V DD or to 0V - Static power dissipation may not be zero - Signals may degrade unacceptably if multiple gates are cascaded - “resistor” often implemented with a transistor to reduce area but signal swing and power dissipation problems still persist A B Y R - Pass transistor logic is widely used Review from Last Time

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

### Page1 / 49

EE 330 Lect 6 Spring 2011 - EE 330 Lecture 6 Improved...

This preview shows document pages 1 - 12. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online