EE 330 Lect 7 Fall 2011

EE 330 Lect 7 Fall 2011 - EE 330 Lecture 7 Delay...

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EE 330 Lecture 7 Delay Calculations Stick Diagrams Technology Files - Design Rules
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MOS Transistor Qualitative Discussion of n-channel Operation Drain Gate Source Bulk Gate Drain Source Bulk n-channel MOSFET Insulator Gate Drain Source Bulk n-channel MOSFET Insulator Resistor For V GS small For V GS large Review from Last Time Gate Drain Source Bulk Insulator
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V GS R SW C GS S D G Improved Switch-Level Model Switch-level model including gate capacitance and drain resistance Switch closed for V GS =“1” C GS and R SW dependent upon device sizes and process For minimum-sized devices in a 0.5u process 1.5fF C GS channel p 6KΩ channel n 2KΩ R sw Considerable emphasis will be placed upon device sizing to manage C GS and R SW Drain Gate Source Review from Last Time
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V G S R SW C GS S D G Model Summary Drain Gate Source D S G = 0 D S G = 1 Switch closed for V GS = large 1, Switch-Level model 2, Improves switch-level model Other models will be developed later Switch open for V GS = small Review from Last Time
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Response time of logic gates (inverter) With improved model HL SWn L t R C LH SWp L t R C A Y C L - Logic Circuits can operate very fast - Extremely small parasitic capacitances play key role in speed of a circuit Review from Last Time
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Summary: What is the delay of a minimum-sized inverter driving a 1pF load? HL SWn L t R C 2 1 2 sec K pF n LH SWp L t R C 6 1 6 K n X Y X Y 1pF Review from Last Time
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V G S R SW C GS S D G Drain Gate Source Switch closed for V GS = large Improved switch-level model Previous example showed why R SW in the model was important But of what use is the C GS which did not enter the previous calculations? Switch open for V GS = small For minimum-sized devices in a 0.5u process 1.5fF C GS channel p 6KΩ channel n 2KΩ R sw
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A Y What are t HL and t LH ?
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EE 330 Lect 7 Fall 2011 - EE 330 Lecture 7 Delay...

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