EE 330 Lect 7 Spring 2011

EE 330 Lect 7 - EE 330 Lecture 7 Technology Files Design Rules Quiz 6 Determine the LH propagation time if a minimum-sized CMOS inverter is driving

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EE 330 Lecture 7 Technology Files - Design Rules
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Quiz 6 Determine the LH propagation time if a minimum-sized CMOS inverter is driving a capacitive load of 200pF. Use typical values for modeling the CMOS inverter but state what values you use. A Y 100pf
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Quiz 6 Determine the LH propagation time if a minimum-sized CMOS inverter is driving a capacitive load of 200pF. Use typical values for modeling the CMOS inverter but state what values you use. A Y 100pf Solution: V GS R SW C GS S D G 1.5fF C GS channel p 6KΩ channel n 2KΩ R sw
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Quiz 6 Determine the LH propagation time if a minimum-sized CMOS inverter is driving a capacitive load of 200pF. Use typical values for modeling the CMOS inverter but state what values you use. A Y 100pf Solution: V GS R SW C GS S D G LH SWp L t =R C LH t =6K 100pF=0.6usec
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MOS Transistor Qualitative Discussion of n-channel Operation Drain Gate Source Bulk Gate Drain Source Bulk n-channel MOSFET Insulator Gate Drain Source Bulk n-channel MOSFET Insulator Resistor For V GS small For V GS large Review from Last Time
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V GS R SW C GS S D G Improved Switch-Level Model Switch-level model including gate capacitance and drain resistance Switch closed for V GS =“1” C GS and R SW dependent upon device sizes and process For minimum-sized devices in a 0.5u process 1.5fF C GS channel p 6KΩ channel n 2KΩ R sw Considerable emphasis will be placed upon device sizing to manage C GS and R SW Drain Gate Source Review from Last Time
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V G S R SW C GS S D G Model Summary Drain Gate Source D S G = 0 D S G = 1 Switch closed for V GS = large 1, Switch-Level model 2, Improves switch-level model Other models will be developed later Switch open for V GS = small Review from Last Time
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EE 330 Lect 7 - EE 330 Lecture 7 Technology Files Design Rules Quiz 6 Determine the LH propagation time if a minimum-sized CMOS inverter is driving

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