EE 330 Lect 8 Spring 2011

EE 330 Lect 8 Spring 2011 - EE 330 Lecture 8 IC Fabrication...

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EE 330 Lecture 8 IC Fabrication Technology Part 1
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Quiz 7 The layout of the cascade of two CMOS inverters is shown. It has some layout errors. Identify them.
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And the number is …. 6 3 1 2 4 5 7 8 9
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And the number is …. 6 3 1 2 4 5 7 8 9 4
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Quiz 7 Solution: - Bulk Connection on P-well is missing - Poly from first gate is shorted to poly from second gate (circuit error, not DRC
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Quiz 7 solution: - Corrected Circuit
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Technology Files Provide Information About Process – Process Flow (Fabrication Technology) – Model Parameters – Design Rules Serve as Interface Between Design Engineer and Process Engineer Insist on getting information that is deemed important for a design – Limited information available in academia – Foundries often sensitive to who gets access to information – Customer success and satisfaction is critical to foundries Review from Last Time
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Design Rules and Layout – consider transistors Drain Gate Source Drain Gate Source Bulk p-active n-active Poly 1 Metal 1 n-well contact D S G L W Layer Map D S G B Bulk connection needed Single bulk connection can often be used for several (many) transistors Review from Last Time
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Design Rules and Layout – consider transistors D S G B D S G Drain Gate Source p-active n-active Poly 1 Metal 1 n-well contact Layer Map Bulk connection needed Single bulk connection can often be used for several (many) transistors is they share the same well Drain Gate Source Bulk Review from Last Time
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Design Rules • Design rules can be given in absolute dimensions for every rule • Design rules can be parameterized and given relative to a parameter – Makes movement from one process to another more convenient – Easier for designer to remember – Some penalty in area efficiency – Often termed λ-based design rules – Typically λ is ½ the minimum feature size in a process Review from Last Time
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EE 330 Lect 8 Spring 2011 - EE 330 Lecture 8 IC Fabrication...

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