EE 330 Lect 16 Fall 2011

EE 330 Lect 16 Fall 2011 - EE 330 Lecture 16 MOS Device...

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EE 330 Lecture 16 MOS Device Modeling p-channel … n-channel comparisons Model consistency and relationships CMOS Process Flow
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Operation Regions by Applications 0 50 100 150 200 250 300 0 1 2 3 4 5 Id Vds Saturation Region Triode Region Cutoff Region Analog Circuits Digital Circuits D I DS V Most analog circuits operate in the saturation region (basic VVR operates in triode and is an exception) Most digital circuits operate in triode and cutoff regions and switch between these two with Boolean inputs Review from Last Time
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0 50 100 150 200 250 300 0 1 2 3 4 5 Id Vds Analog Circuits D I DS V Output Impedance Model in Saturation Region ( ) [ ] 1 2 D OX GS T DS W I=μC V V 2L λV −+ In saturation region ( ) ( )    22 D OX GS T O S X GS T D WW V V μC V V 2L λV 2L ( ) 2 D OX D Q ST S DE G W I 1 V R =μC V V 2L ( ) 1 DEQ 2 OX GS T R= W μC V V 2 λ L Review from Last Time
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Model Status Simple dc Model Small Signal Frequency Dependent Small Signal Better Analytical dc Model Sophisticated Model for Computer Simulations Simpler dc Model Square-Law Model Square-Law Model (with extensions for λ,γ effects) Short-Channel α-law Model BSIM Model Switch-Level Models • Ideal switches • R SW and C GS Review from Last Time
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In the next few slides, the models we have developed will be listed and reviewed Square-law Model Switch-level Models Extended Square-law model Short-channel model BSIM Model BSIM Binning Model Corner Models Review from Last Time
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Square-Law Model I D V DS ( ) GS T DS D OX GS T DS GS DS GS T 2 OX GS T GS T DS GS T 0 VV V W I μ C V V V V L2 W μ C V V V 2L T  = −− <   ≥− V GS1 V GS3 V GS2 V GS4 Review from Last Time Model Parameters : {μ,C OX ,V T0 } Design Parameters : {W,L} but only one degree of freedom W/L
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V GS R SW C GS S D G Switch-Level Models Switch-level model including gate capacitance and drain resistance Switch closed for V GS =“1” C GS and R SW dependent upon device sizes and process For minimum-sized devices in a 0.5u process 1.5fF C GS channel p 6KΩ channel n 2KΩ R sw Considerable emphasis will be placed upon device sizing to manage C GS and R SW Drain Gate Source Review from Last Time Model Parameters : {C GS ,R SW }
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Extended Square-Law Model ( ) ( ) 1 GS T DS D OX GS T DS GS DS GS T 2 OX GS T DS GS T DS GS T 0 VV V W I μ C V V V V L2 W μ C V V V V 2L T λ  = −− <   •+ ( ) φ γ + = BS T0 T V V V Model Parameters : {μ,C OX ,V T0 ,φ,γ,λ} Design Parameters : {W,L} but only one degree of freedom W/L 0 I 0 I B G = = Review from Last Time
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Short-Channel Model ( ) ( ) ( ) ( ) 1 1 GS T 2 22 D OX GS T DS GS DS GS 1 2 2 OX GS T GS T DS GS 0 VV W I μC V V V V V V V L W μC V V V V V V L TT T V V αα α θ θθ = <− ≥− α is the velocity saturation index, 2 ≥ α ≥ 1
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EE 330 Lect 16 Fall 2011 - EE 330 Lecture 16 MOS Device...

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