EE 330 Lect 23 Spring 2011

EE 330 Lect 23 - EE 330 Lecture 23 Thyristors Review from Last Lecture The JFET G D G S n-channel G D S D S p-channel p-channel JFET Square-law

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EE 330 Lecture 23 Thyristors
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The JFET S D G GS P DSS DS D GS P DS GS P DS GS P 2 P 2 GS DSS GS P DS GS P P 0 VV 2I V I V -V - V V V V < V -V V2 V I 1- V V V < V -V V <  = >   > D D S S G G n-channel p-channel p-channel JFET Square-law model of n-channel JFET Functionally identical to the square-law model of MOSFET Parameters I DSS and V P characterize the device I DSS proportinal to W/L where W and L are width and length of n+ diff V P is negative for n-channel device, positive for p-channel device thus JFET is depletion mode device Must not forward bias GS junction by over about 300mV or excessive base current will flow Review from Last Lecture
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The Thyristor S G D G S D Consider a Bulk-CMOS Process A bipolar device in CMOS Processes Have formed a lateral pnpn device ! Review from Last Lecture
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The SCR S ilicon C ontrolled R ectifier • Widely used to switch large resistive or inductive loads • Widely used in the power electronics field • Widely used in consumer electronic to interface between logic and power Anode Cathode Gate G C A p p n n G G G A A A C C C Symbols Consider first how this 4-layer 3-junction device operates Usually made by diffusions in silicon Review from Last Lecture
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Operation of the SCR C G A Q 1 Q 2 I F I G I C1 I B2 I C2 I B1 G C A p p n n G C A p n n p n p C 1 B 1 E 1 C 2 B 2 E 2 G A C V F V G I F I G Not actually separated but useful for describing operation Review from Last Lecture
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Operation of the SCR I F V F I G =0 BGF1 V I H I F V F I G =I G1 >0 BGF0 V I H The Ideal SCR G A C V F V G I F I G I H is very small I G1 is small (but not too small) ( ) , F FG I = f V V ( ) , F called the SCR model As for MOSFET, Diode, and BJT, several models for SCR can be developed Review from Last Lecture
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Operation of the SCR Operation with the Ideal SCR V CC V G R L V F I F I F V F I G =0 CC V CC L V R Load Line I H Now assume it was initially in the OFF state and then a gate current was applied CC F L F V = I R +V ( ) , FI F G I = f V V Now there is a single intersection point so a unique solution The SCR is now ON I F V F CC V CC L V R Load Line I H I G =I G1 >0 Removing the gate current will return to the previous solution but it will remain in the ON state Review from Last Lecture
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Operation of the SCR Operation with the Ideal SCR Duty cycle control of R L V AC V G R L V F I F t V AC V LOAD I GATE
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Operation of the SCR Operation with the Ideal SCR Duty cycle control of R L V AC V G R L V F I F V LOAD I GATE V LOAD I GATE
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I F V F I G =0 F ΔV BRF0 V BRR V I H G A C V F V G I F I G Operation of the SCR Operation with the actual SCR
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I F V F I G4 >I G3 >I G2 >I G1 =0 V BRR I H BRF0 V G A C V F V G I F I G Operation of the SCR Operation with the actual SCR
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EE 330 Lect 23 - EE 330 Lecture 23 Thyristors Review from Last Lecture The JFET G D G S n-channel G D S D S p-channel p-channel JFET Square-law

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