{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

EE 330 Lect 23 Spring 2011

EE 330 Lect 23 Spring 2011 - EE 330 Lecture 23 Thyristors...

Info icon This preview shows pages 1–12. Sign up to view the full content.

View Full Document Right Arrow Icon
EE 330 Lecture 23 Thyristors
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
The JFET S D G GS P DSS DS D GS P DS GS P DS GS P 2 P 2 GS DSS GS P DS GS P P 0 V V 2I V I V -V - V V V V < V -V V 2 V I 1- V V V < V -V V < = > > D D S S G G n-channel p-channel p-channel JFET Square-law model of n-channel JFET Functionally identical to the square-law model of MOSFET Parameters I DSS and V P characterize the device I DSS proportinal to W/L where W and L are width and length of n+ diff V P is negative for n-channel device, positive for p-channel device thus JFET is depletion mode device Must not forward bias GS junction by over about 300mV or excessive base current will flow Review from Last Lecture
Image of page 2
The Thyristor S G D G S D Consider a Bulk-CMOS Process A bipolar device in CMOS Processes Have formed a lateral pnpn device ! Review from Last Lecture
Image of page 3

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon