EE 330 Lect 38 Spring 2011

EE 330 Lect 38 Spring 2011 - EE 330 Lecture 38 Digital...

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EE 330 Lecture 38 Digital Circuits Characterization of the CMOS Inverter
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Desirable and/or Required Logic Family Characteristics 1. High and low logic levels must be uniquely distinguishable (even in a long cascade) 2. Capable of driving many loads (good fanout) 3. Fast transition times (but in some cases, not too fast) 4. Good noise margins (low error probabilities) 5. Small die area 6. Low power consumption 7. Economical process requirements Review from Last Time
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Desirable and/or Required Logic Family Characteristics 8. Minimal noise injection to substrate 9. Low leakage currents 10. No oscillations during transitions 11. Compatible with synthesis tools 12. Characteristics do not degrade too much with temperature 13. Characteristics do not vary too much with process variations Are some of these more important than others? Yes ! – must have well-defined logic levels for circuits to even function as logic Review from Last Time
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Desirable and/or Required Logic Family Characteristics Are some of these more important than others? Yes ! – must have well-defined logic levels for circuits to even function as logic What are the logic levels for a given inverter of for a given logic family? What properties of an inverter are necessary for it to be useful for building a logic family Review from Last Time
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What are the logic levels for a given inverter of for a given logic family? V H =? V L =? Can we legislate them ? Some authors choose to simply define a value for them Simple and straightforward approach But what if the circuit does not interpret them the same way they are defined !! Review from Last Time
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Observation V IN V OUT V’ OUT V’ OUT V IN V L V H V TRIP 1 1 When V OUT =V IN for the inverter, V’ OUT is also equal to V IN . Thus the intersection point for V OUT =V IN in the inverter transfer characteristics (ITC) is also an intersection point for V’ OUT =V IN in the inverter-pair transfer characteristics (IPTC) V OUT V IN V TRIP 1 1 Review from Last Time
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Transfer characteristics of the static CMOS inverter IN V OUT V M 1 M 2 V DD V IN V OUT Review from Last Time
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M 1 M 2 V DD V IN V OUT
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Transfer characteristics of the static CMOS inverter M 1 M 2 V DD V IN V OUT Case 1 M 1 triode, M 2 cutoff OUT 1 D1 n OXn IN Tn OUT 1 V W IμC V V V L2  = −−   GS1 Tn DS1 GS1 Tn V V V VV <− 0 D2 I = 0 OUT 1 n OXn IN Tn OUT 1 V W μC V V V = 0 OUT V = GS2 Tp Equating I D1 and –I D2 we obtain: It can be shown that setting the first product term to 0 will not verify, thus valid for: IN Tn OUT IN Tn V V V IN DD Tp V −≥ thus, valid for: (Neglect λ effects)
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GS1 Tn DS1 GS1 Tn V V V VV <− GS2 Tp IN Tn OUT IN Tn V V V IN DD Tp V −≥
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Transfer characteristics of the static CMOS inverter Case 1 M 1 triode, M 2 cutoff 0 OUT V = OUT IN Tn V VV <− IN DD Tp V −≥ IN Tn V DD V DD V IN V OUT -V Tp -V Tn V DD +V Tp M 2 CO M 1 CO M 1 TR M 1 SAT (Neglect λ effects)
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Transfer characteristics of the static CMOS inverter Case 1 M 1 triode, M 2 cutoff 0 OUT V = OUT IN Tn V VV <− IN DD Tp V −≥
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EE 330 Lect 38 Spring 2011 - EE 330 Lecture 38 Digital...

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