EE 330 Lect 39 Spring 2011

EE 330 Lect 39 Spring 2011 - EE 330 Lecture 39 Digital...

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EE 330 Lecture 39 Digital Circuits Multiple-input gates Propagation Delay – basic characterization Device Sizing
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Transfer characteristics of the static CMOS inverter V DD V DD V IN V OUT -V Tp V Tn V DD +V Tp Case 1 Case 2 Case 3 Case 4 Case 5 (Neglect λ effects) Review from Last Time M 1 M 2 V DD V IN V OUT
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Transfer characteristics of the static CMOS inverter V DD V DD V IN V OUT -V Tp V Tn V DD +V Tp V TRIP 1 1 (Neglect λ effects) ( ) ( ) 1 p 21 Tn DD Tp n 12 IN p n μ WL V V +V μ WL V μ + = + From Case 3 analysis: Review from Last Time
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Inverter Transfer Characteristics of Inverter Pair IN V OUT V What are V H and V L ? Find the points on the inverter pair transfer characteristics where V OUT ’=V IN and the slope is less than 1 V’ OUT V IN V L V H V TRIP Review from Last Time
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Inverter Transfer Characteristics of Inverter Pair for THIS Logic Family IN V OUT V V DD V DD V IN V OUT -V Tp -V Tn V DD +V Tp V TRIP 1 1 V DD V DD V IN V OUT -V Tp -V Tn V DD +V Tp V TRIP 1 1 V DD V DD V IN V’ OUT -V Tp -V Tn V DD +V Tp V L V H V TRIP V H =V DD and V L =0 Note this is independent of device sizing for THIS logic family !! M 1 M 2 V DD V IN V OUT Review from Last Time
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How should M 1 and M 2 be sized? M 1 M 2 V DD V IN V OUT How many degrees of freedom are there in the design of the inverter? { W 1 ,W 2 ,L 1 ,L 2 } 4 degrees of freedom But in basic device model and in most performance metrics, W 1 /L 1 and W 2 /L 2 appear as ratios { W 1 /L 1 ,W 2 /L 2 } effectively 2 degrees of freedom Review from Last Time
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How should M 1 and M 2 be sized? M 1 M 2 V DD V IN V OUT One popular sizing strategy: 1. Pick W 1 =W MIN to minimize area of M 1 2. Pick W 2 to set trip-point at V DD /2 pick L 1 =L 2 =L min V DD V DD V IN V OUT -V Tp V Tn V DD +V Tp V TRIP 1 1 ( ) ( ) 1 p 21 Tn DD Tp n 12 OUT IN TRIP p n μ WL V V +V μ WL V =V V μ + = = + Observe Case 3 provides expression for V TRIP Thus, at the trip point, Review from Last Time
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How should M 1 and M 2 be sized? M 1 M 2 V DD V IN V OUT One popular sizing strategy: 1. Pick W 1 =W MIN to minimize area of M 1 2. Pick W 2 to set trip-point at V DD /2 pick L 1 =L 2 =L min ( ) ( ) 1 p 21 Tn DD Tp n 12 TRIP p n μ WL V V +V μ WL V μ + = + Typically V Tn =0.2V DD , |V Tp |=0.2V DD ( ) ( ) 1 p 2 DD DD DD n1 DD p 2 μ W 0.2V V -0.2V μW V 2 μ W + = + Solving this equation for W 2 , obtain n p μ WW μ  =   Other sizing strategies are used as well and will be discussed later ! Review from Last Time
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Extension of Basic CMOS Inverter to Multiple-Input Gates V DD Y A B M 2 M 1 M 4 M 3 A B Y 0 0 1 0 1 0 1 0 0 1 1 0 Truth Table A B Y Performs as a 2-input NOR Gate Can be easily extended to an n-input NOR Gate
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Extension of Basic CMOS Inverter to Multiple-Input Gates A B Y 0 0 1 0 1 1 1 0 1 1 1 0 Truth Table V DD Y A B M 2 M 1 M 4 M 3 A B Y Performs as a 2-input NAND Gate Can be easily extended to an n-input NAND Gate
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Static CMOS Logic Family V IN V OUT V DD M 1 M 2 V IN V OUT V DD M 1 M 2 Pull-up Network PUN Pull-down Network PDN Observe PUN is p-channel, PDN is n-channel
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EE 330 Lect 39 Spring 2011 - EE 330 Lecture 39 Digital...

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