EE 330 Lect 40 Fall 2011

EE 330 Lect 40 Fall - EE 330 Lecture 40 Digital Circuits Device Sizing Review from Last Time Static Power Dissipation in Static CMOS Family VDD M2

Info iconThis preview shows pages 1–9. Sign up to view the full content.

View Full Document Right Arrow Icon
EE 330 Lecture 40 Digital Circuits Device Sizing
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Static Power Dissipation in Static CMOS Family When V OUT is Low, I D1 =0 When V OUT is High, I D2 =0 Thus, P STATIC =0 This is a key property of the static CMOS Logic Family and is the major reason Static CMOS Logic is so dominant It can be shown that this zero static power dissipation property can be preserved if the PUN is comprised of n-channel devices, the PDN is comprised of n-channel devices and they are never both driven into the conducting states at the same time M 1 M 2 V DD V IN V OUT Review from Last Time
Background image of page 2
Static Power Dissipation in Ratio Logic Families V IN V OUT V DD M 1 M 2 Enhancement Load NMOS Example: Assume V DD =5V V T =1V, μC OX =10 -4 A/V 2 , W 1 /L 1 =1 and M 2 sized so that V L =V Tn P L =(5V)(0.25mA)=1.25mW If a circuit has 100,000 gates and half of them are in the V OUT =V L state, the static power dissipation will be 62.5W mW P STATIC 25 . 1 10 2 1 5 This power dissipation is way too high and would be even larger in circuits with 100 million or more gates – the level of integration common in SoC circuits today Review from Last Time
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Propagation Delay in Static CMOS Family V IN V OUT C L V G R PU V OUT C L V DD For HL output transition, C L charged to V DD V DD V IN t t=0 V DD V OUT t=0 t (1-e -1 )V DD t 2 V TRIP HL PD L t R C LH 2 PU L t t =R C Summary: LH PU L t R C Review from Last Time
Background image of page 4
Propagation Delay in Static CMOS Family F A Propagation through k levels of logic   HL HLk LH(k-1) XY1 HL k-2 t t + t + t + ••• + t   LH LHk HL(k-1) YX1 LH k-2 t t + t + t + ••• + t where x=H and Y=L if k odd and X=L and Y=h if k even 1 PROP PROPk t t k i Review from Last Time
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Device Sizing Minimum Size Fixed V TRIP Equal rise-fall times (equal worst-case rise and fall times) Minimum power dissipation Minimum time required to drive a given load Minimum input capacitance Sizing Strategies Since not ratio logic, V H and V L are independent of device sizes for this inverter With L 1 =L 2 =L min , there are 2 degrees of freedom (W 1 and W 2 ) M 1 M 2 V DD V IN V OUT C L Review from Last Time
Background image of page 6
Device Sizing Sizing Strategy Summary Minimum Size V TRIP =V DD /2 Equal Rise/Fall Size W n =W p =W min L p =L n =L min W n =W min W p= 3W min L p =L n =L min W n =W min W p= 3W min L p =L n =L min t HL R pd C L R pd C L R pd C L t LH 3R pd C L R pd C L R pd C L t PROP 4R pd C L 2R pd C L 2R pd C L V trip V TRIP =0.42V DD V TRIP =0.5V DD V TRIP =0.5V DD M 1 M 2 V DD V IN V OUT C L Assume V Tn =0.2V DD , V Tp =-0.2V DD , μ n p =3, L 1 =L 2 =L min For a fixed load C L , the minimum-sized structure has a higher t PROP but if the load is another inverter, C L will also increase so the speed improvements become less apparent This will be investigated later Review from Last Time
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
The Reference Inverter REF IN OX MIN MIN C =C = 4C W L REF HLREF LHREF PDREF t = t + t = 2R C     .2 MIN MIN PDREF n OX MIN DD Tn n OX MIN DD LL R μ C W V -V μ C W 0.8V Tn DD VV  V IN V OUT M 1 M 2 V DD W n =W MIN , W p =3W MIN Assume μ n / μ p
Background image of page 8
Image of page 9
This is the end of the preview. Sign up to access the rest of the document.

This document was uploaded on 01/31/2012.

Page1 / 32

EE 330 Lect 40 Fall - EE 330 Lecture 40 Digital Circuits Device Sizing Review from Last Time Static Power Dissipation in Static CMOS Family VDD M2

This preview shows document pages 1 - 9. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online