EE 330
Lecture 40
Digital Circuits
Device Sizing
This
preview
has intentionally blurred sections.
Sign up to view the full version.
Static Power Dissipation in Static CMOS Family
When V
OUT
is Low, I
D1
=0
When V
OUT
is High, I
D2
=0
Thus, P
STATIC
=0
This is a key property of the static CMOS Logic
Family and is the major reason Static CMOS Logic is
so dominant
It can be shown that this zero static power dissipation
property can be preserved if the PUN is comprised of
n-channel devices, the PDN is comprised of n-channel
devices and they are never both driven into the conducting
states
at the same time
M
1
M
2
V
DD
V
IN
V
OUT
Review from Last Time