EE 330 Lect 40 Spring 2011

# EE 330 Lect 40 Spring 2011 - EE 330 Lecture 40 Digital...

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EE 330 Lecture 40 Digital Circuits Device Sizing

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Other CMOS Logic Families V IN V OUT V DD M 2 M 1 Depletion Load NMOS V DD V OUT V IN V DD V TD <0 • Reduced V H -V L • Device sizing critical for even basic operation • Shallow slope at V TRIP V DD V DD V IN V’ OUT -V Tp -V Tn V DD V DD V IN V’ OUT -V Tp -V Tn Review from Last Time
Static Power Dissipation in Static CMOS Family When V OUT is Low, I D1 =0 When V OUT is High, I D2 =0 Thus, P STATIC =0 This is a key property of the static CMOS Logic Family and is the major reason Static CMOS Logic is so dominant It can be shown that this zero static power dissipation property can be preserved if the PUN is comprised of n-channel devices, the PDN is comprised of n-channel devices and they are never both driven into the conducting states at the same time M 1 M 2 V DD V IN V OUT Review from Last Time

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Static Power Dissipation in Ratio Logic Families V IN V OUT V DD M 1 M 2 Enhancement Load NMOS Example: Assume V DD =5V V T =1V, μC OX =10 -4 A/V 2 , W 1 /L 1 =1 and M 2 sized so that V L =V Tn P L =(5V)(0.25mA)=1.25mW If a circuit has 100,000 gates and half of them are in the V OUT =V L state, the static power dissipation will be 62.5W = = mW P STATIC 25 . 1 10 2 1 5 This power dissipation is way too high and would be even larger in circuits with 100 million or more gates – the level of integration common in SoC circuits today Review from Last Time
Propagation Delay in Static CMOS Family V IN V OUT C L V G R PU V OUT C L V DD For HL output transition, C L charged to V DD V DD V IN t t=0 V DD V OUT t=0 t (1-e -1 )V DD t 2 V TRIP HL PD L t RC LH 2 PU L t t =R C Summary: LH PU L t Review from Last Time

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Propagation Delay in Static CMOS Family F A Propagation through k levels of logic ( ) HL HLk LH(k-1) XY1 HL k-2 t t + t + t + ••• + t ( ) LH LHk HL(k-1) YX1 LH k-2 t t + t + t + ••• + t where x=H and Y=L if k odd and X=L and Y=h if k even 1 PROP PROPk t t k i = = Review from Last Time
Digital Circuit Design Hierarchical Design Basic Logic Gates Properties of Logic Families Characterization of CMOS Inverter Static CMOS Logic Gates – Ratio Logic Propagation Delay – Simple analytical models – Elmore Delay Sizing of Gates Propagation Delay with Multiple Levels of Logic Optimal driving of Large Capacitive Loads Power Dissipation in Logic Circuits Other Logic Styles Array Logic Ring Oscillators done partial

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Device Sizing Degrees of Freedom? Strategies? V OUT V DD A 1 A 2 A k A 1 A 2 A k M 11 M 12 M 1k M 21 M 22 M 2k V OUT M 1k M 21 V DD A 1 A 2 A k M 22 M 2k A 1 A 2 A k M 2k M 1k Will consider the inverter first M 1 M 2 V DD V IN V OUT
Device Sizing Degrees of Freedom? Strategies? M 1 M 2 V DD V IN V OUT C L

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Device Sizing Minimum Size Fixed V TRIP Equal rise-fall times (equal worst-case rise and fall times) Minimum power dissipation Minimum time required to drive a given load Minimum input capacitance Sizing Strategies Since not ratio logic, V H and V L are
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EE 330 Lect 40 Spring 2011 - EE 330 Lecture 40 Digital...

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