EE 330 Lect 42 Fall 2011

EE 330 Lect 42 Fall 2011 - EE 330 Lecture 42 Digital...

Info iconThis preview shows pages 1–8. Sign up to view the full content.

View Full Document Right Arrow Icon
EE 330 Lecture 42 Digital Circuits Overdrive Propagation Delay in Multiple Levels of Logic Optimally Driving Large Capacitive Loads
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Device Sizing IN REF C =C Assume μ n p =3 L n =L p =L MIN W n =W MIN , W p =3W MIN Equal Worse-Case Rise/Fall Device Sizing Strategy -- (same as V TRIP =V DD /2 in typical process considered in example) k-input NOR INV k-input NOR W n =W MIN , W p =3kW MIN W n =kW MIN , W p =3W MIN IN REF 3k+1 C = C 4    IN REF 3+k C = C 4 V IN V OUT M 1 M 2 V DD C REF V OUT M 1k M 21 V DD A 1 A 2 A k M 22 M 2k A 1 A 2 A k M 2k M 1k C REF V OUT V DD A 1 A 2 A k A 1 A 2 A k M 11 M 12 M 1k M 21 M 22 M 2k C REF FI=1 3k+1 FI= 4 3+k FI= 4 Review from last lecture
Background image of page 2
Device Sizing – minimum size driving C REF k-input NAND INV k-input NOR PROP t? PROP PROP 3 t 0.5 2 REF REF k tt  PROP 31 t 2 REF k t    PROP 3 t 22 REF REF k PROP 3 t 2 REF k t REF C FI = 2 REF C FI = 2 3 PU PDREF R kR PD PDREF RR  PU PD PDREF R R R 3 PD PDREF 3 PU PDREF V OUT M 1k M 21 V DD A 1 A 2 A k M 22 M 2k A 1 A 2 A k M 2k M 1k C REF V IN V OUT M 1 M 2 V DD C REF V OUT V DD A 1 A 2 A k A 1 A 2 A k M 11 M 12 M 1k M 21 M 22 M 2k C REF REF C FI = 2 PROP PROP t2 REF t PROP 3 t 0.5 2 REF REF Review from last lecture
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Propagation Delay in Multiple- Levels of Logic with Stage Loading Analysis strategy : Express delays in terms of those of reference inverter REF IN OX MIN MIN C =C = 4C W L REF HLREF LHREF PDREF t =t +t =2R C     .2 MIN MIN PDREF n OX MIN DD Tn n OX MIN DD LL R μ C W V -V μ C W 0.8V Tn DD VV  V IN V OUT M 1 M 2 V DD W n =W MIN , W p =3W MIN Assume μ n / μ p =3 Reference Inverter L n =L p =L MIN In 0.5u proc t REF =20ps, C REF =4fF,R PDREF =2.5K FI= 1 Review from last lecture
Background image of page 4
Propagation Delay with Stage Loading REF IN OX MIN MIN C =C = 4C W L REF PDref REF t =2R C V IN V OUT FI of a capacitor FI of a gate (input k) C REF C FI = C INk G REF C FI = C INI I REF C FI = C FI of an interconnect Overall FI INGi INCi INIi Gates Capacitances Interconnects FI= C + C + C FI can be expressed either in units of capacitance or normalized to C REF Most commonly FI is normalized but must determine from context Review from last lecture
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Propagation Delay Through Multiple Stages of Logic with Stage Loading G 1 G 2 G 3 G n A F F I2 F I3 F I4 F I(n+1) G xx G x2 G x3 G x4 t PROPk =t REF FI (k+1) Propagation delay from A to F: n PROP REF (k+1) k=1 t =t FI (assuming gate drives are all same as that of reference inverter) Identify the gate path from A to F Review from last lecture
Background image of page 6
Digital Circuit Design Hierarchical Design Basic Logic Gates Properties of Logic Families Characterization of CMOS Inverter Static CMOS Logic Gates Ratio Logic Propagation Delay Simple analytical models Elmore Delay Sizing of Gates Propagation Delay with Multiple Levels of Logic Optimal driving of Large Capacitive Loads Power Dissipation in Logic Circuits Other Logic Styles Array Logic Ring Oscillators done partial
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 8
This is the end of the preview. Sign up to access the rest of the document.

This document was uploaded on 01/31/2012.

Page1 / 43

EE 330 Lect 42 Fall 2011 - EE 330 Lecture 42 Digital...

This preview shows document pages 1 - 8. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online