EE 330 Lect 42 Spring 2011

EE 330 Lect 42 Spring 2011 - EE 330 Lecture 42 Digital...

Info iconThis preview shows pages 1–6. Sign up to view the full content.

View Full Document Right Arrow Icon
EE 330 Lecture 42 Digital Circuits Device Sizing Propagation Delay in Multiple Levels of Logic Optimally Driving Large Capacitive Loads
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Propagation Delay How does the propagation delay compare for a minimum-sized strategy to that of an equal rise/fall sizing strategy? V IN V OUT M 1 M 2 V DD M 1 M 2 V DD C L V’ OUT C L1 V IN V OUT M 1 M 2 V DD M 1 M 2 V DD C L V’ OUT C L1 Minimum Sized Reference Inverter W 2 =W 1 =W MIN W 2 =(μ n p )W 1 , W 1 =W MIN PROP REF t = t PROP REF t = t Even though the t LH rise time has been reduced with the equal rise/fall sizing strategy, this was done at the expense of an increase in the total load capacitance that resulted in no net change in propagation delay! They are the same! Review from last lecture
Background image of page 2
Device Sizing V IN V OUT M 1 M 2 V DD V OUT V DD A 1 A 2 A k A 1 A 2 A k M 11 M 12 M 1k M 21 M 22 M 2k V OUT M 1k M 21 V DD A 1 A 2 A k M 22 M 2k A 1 A 2 A k M 2k M 1k Will consider now the multiple-input gates Will consider both minimum sizing and equal worst-case rise/fall Will assume C L (not shown)=C REF Note: worst-case has been added since fall time in NOR gates or rise time in NAND gates depends upon how many transistors are conducting Review from last lecture
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Sizing of Multiple-Input Gates Analysis strategy : Express delays in terms of those of reference inverter REF IN OX MIN MIN C =C = 4C W L REF HLREF LHREF PDREF t = t + t = 2R C     .2 MIN MIN PDREF n OX MIN DD Tn n OX MIN DD LL R μ C W V -V μ C W 0.8V Tn DD VV  V IN V OUT M 1 M 2 V DD W n =W MIN , W p =3W MIN Assume μ n p =3 Reference Inverter Ln=Lp=L MIN In 0.5u proc t REF =20ps, C REF =4fF,R PDREF =2.5K t = t =R C Review from last lecture
Background image of page 4
Device Sizing V IN V OUT M 1 M 2 V DD V OUT M 1k M 21 V DD A 1 A 2 A k M 22 M
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 6
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 19

EE 330 Lect 42 Spring 2011 - EE 330 Lecture 42 Digital...

This preview shows document pages 1 - 6. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online