EE 330 Lect 43 Fall 2011

# EE 330 Lect 43 Fall 2011 - EE 330 Lecture 43 Digital...

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EE 330 Lecture 43 Digital Circuits Optimally Driving Large Capacitive Loads Logical Effort Elmore Delay Power Dissipation

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Propagation Delay with Over-drive Capability C L =900C REF V IN V OUT Example C L =900C REF V IN V OUT 900 C L =900C REF V IN V OUT 30 Compare the propagation delays. Assume the OD is 900 in the second case and 30 in the third case  PROP REF REF REF t =t 900t 901t REF REF REF t =900t t REF REF REF t =30t 30t 60t Note: Dramatic reduction in t PROP is possible Will later determine what optimal number of stages and sizing is Review from last lecture
Propagation Delay in Multiple-Levels of Logic with Stage Loading Asymmetric-sized gates C IN /C REF Equal Rise/Fall Inverter NAND NOR 1 3k+1 4 3+k 4 Minimum Sized Overdrive HL LH 1 1 1/2 1/2 1/2 1 1/3 NOR NAND Inverter HL LH HL LH 1 1 1 1 1 1/(3k) 1/k 1/3 Equal Rise/Fall (with OD) OD 3k+1 OD 4 3+k OD 4 Asymmetric OD (OD HL , OD LH ) HL LH OD +3 OD 4 OD OD OD OD OD OD HL LH OD +3k OD 4 HL LH k OD +3 OD 4  OD HL OD LH OD HL OD LH OD HL OD LH n I(k+1) k=1 k F OD n I(k+1) k=1 F 1    n I(k+1) k=1 HLk LHk 11 F 2 OD OD t PROP /t REF 1 n I(k+1) k=1 HLk LHk F 2 OD OD OD H OD L 1  5 PROP REF I(k+1) k=1 HLk LHk t =t F 2 OD OD Review from last lecture

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Propagation Delay in Multiple- Levels of Logic with Stage Loading n I(k+1) PROP REF k=1 k F t =t OD Equal rise/fall (no overdrive) Equal rise/fall with overdrive Minimum Sized Asymmetric overdrive Combination of equal rise/fall, minimum size and overdrive n PROP REF (k+1) k=1 t =t FI G 1 G 2 G 3 G n A F F I2 F I3 F I4 F I(n+1) G xx G x2 G x3 G x4 1     n PROP REF I(k+1) k=1 HLk LHk 11 t =t F 2 OD OD 1 n PROP REF I(k+1) k=1 HLk LHk t =t F 2 OD OD 1 n PROP REF I(k+1) k=1 HLk LHk t =t F 2 OD OD Review from last lecture
A F 4 2 4 2 4 2 1 1 1 1 1 1 1/2 1/4 1 1 4 1/4 1 2 2 1 1 2 1 2 1 2 20fF 50fF 1 2 ? PROP REF t = t Asymmetric-sized gates LH OD = 2 HL OD = 1 7/8 1 1 20fF =5 4fF REF C C HL OD = 12 LH OD = 1/4 F I2 =63/8 7/4 11/2 F I3 =29/4 HL OD = 1 LH OD = 1 F I4 =77/16 HL OD = 4 LH OD = 1/4 25/16 LH OD = 2 HL OD = 4 50fF =12.5 4fF REF C C F I5 =7/2 F I6 =12.5 1     5 PROP REF I(k+1) k=1 HLk LHk 11 t =t F 2 OD OD     63 1 29 77 7 1 1 1 1 2 4 1 1 4 12.5 8 2 4 16 2 4 2 4 PROP REF 1 t =t 2 PROP REF t =44.6 t OD HL OD LH NOR: NAND: 7/2 13/4 Review from last lecture

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Digital Circuit Design Hierarchical Design Basic Logic Gates Properties of Logic Families Characterization of CMOS Inverter Static CMOS Logic Gates Ratio Logic Propagation Delay Simple analytical models FI/OD Logical Effort Elmore Delay Sizing of Gates Propagation Delay with Multiple Levels of Logic Optimal driving of Large Capacitive Loads Power Dissipation in Logic Circuits Other Logic Styles Array Logic Ring Oscillators done partial
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EE 330 Lect 43 Fall 2011 - EE 330 Lecture 43 Digital...

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