EE 330 Lect 43 Spring 2011

# EE 330 Lect 43 Spring 2011 - EE 330 Lecture 43 Digital...

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EE 330 Lecture 43 Digital Circuits Overdrive Propagation Delay in Multiple Levels of Logic Optimally Driving Large Capacitive Loads

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Device Sizing – minimum size driving C REF V IN V OUT M 1 M 2 V DD V OUT M 1k M 21 V DD A 1 A 2 A k M 22 M 2k A 1 A 2 A k M 2k M 1k V OUT V DD A 1 A 2 A k A 1 A 2 A k M 11 M 12 M 1k M 21 M 22 M 2k k-input NOR INV k-input NOR PROP t? PROP PROP 3 t 0.5 2 REF REF k tt  PROP 31 t 2 REF k t    PROP 3 t 22 REF REF k PROP 3 t 2 REF k t Review from last lecture REF C FI = 2 REF C FI = 2
Propagation Delay in Multiple- Levels of Logic with Stage Loading Analysis strategy : Express delays in terms of those of reference inverter REF IN OX MIN MIN C =C = 4C W L REF HLREF LHREF PDREF t =t +t =2R C     .2 MIN MIN PDREF n OX MIN DD Tn n OX MIN DD LL R μ C W V -V μ C W 0.8V Tn DD VV  V IN V OUT M 1 M 2 V DD W n =W MIN , W p =3W MIN Assume μ n p =3 Reference Inverter Ln=Lp=LMIN In 0.5u proc t REF =20ps, C REF =4fF,R PDREF =2.5K Review from last lecture

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Propagation Delay with Stage Loading REF IN OX MIN MIN C =C = 4C W L REF PDref REF t =2R C V IN V OUT FI of a capacitor FI of a gate (input k) C REF C FI = C INk G REF C FI = C INI I REF C FI = C FI of an interconnect Overall FI INGi INCi INIi Gates Capacitances Interconnects FI= C + C + C FI can be expressed either in units of capacitance or normalized to C REF Most commonly FI is normalized but must determine from context Review from last lecture
Propagation Delay Through Multiple Stages of Logic with Stage Loading G 1 G 2 G 3 G n A F F I2 F I3 F I4 F I(n+1) G xx G x2 G x3 G x4 t PROPk =t REF FI (k+1) Propagation delay from A to F: n PROP REF (k+1) k=1 t =t FI (assuming gate drives are all same as that of reference inverter) Identify the gate path from A to F Review from last lecture

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Digital Circuit Design Hierarchical Design Basic Logic Gates Properties of Logic Families Characterization of CMOS Inverter Static CMOS Logic Gates Ratio Logic Propagation Delay Simple analytical models Elmore Delay Sizing of Gates Propagation Delay with Multiple Levels of Logic Optimal driving of Large Capacitive Loads Power Dissipation in Logic Circuits Other Logic Styles Array Logic Ring Oscillators done partial
Overdrive Factors C A F 1000 The factor by which the devices are scaled above those of the reference inverter is termed the overdrive factor, OD Scaling all widths by a constant does not compromise the symmetry between the rise and fall times Judicious use of overdrive can dramatically improve the speed of digital circuits Large overdrive factors are often used

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Propagation Delay with Over-drive Capability C L V IN V OUT OD F IL PDREF PDEFF HL R R= OD Define the Asymmetric Overdrive Factors of the stage to be the factor by which PU and PD resistors are scaled relative to those of the reference inverter.
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EE 330 Lect 43 Spring 2011 - EE 330 Lecture 43 Digital...

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