EE 330 Lect 44 Fall 2011

EE 330 Lect 44 Fall - EE 330 Lecture 44 Digital Circuits Power Dissipation Other Logic Styles High Frequency Device Models Review from last lecture

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EE 330 Lecture 44 Digital Circuits Power Dissipation Other Logic Styles High Frequency Device Models
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Optimal Driving of Capacitive Loads A F C L 1 θ θ 2 θ n-1 n REF L θ C =C   L PROP REF REF C θ t =t ln ln θC    OPT θ = e L OPT REF C n ln C    L PROP REF REF REF C t = t e ln nθt C Review from last lecture
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Optimal Driving of Capacitive Loads θ 2 3 e e minimum at θ=e but shallow inflection point for 2<θ<3   θ f= ln θ practically pick θ=2, θ=2.5, or θ=3 since optimization may provide non-integer for n, must pick close integer Review from last lecture
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Propagation Delay in “Logic Effort” approach n PROP k k=1 t = f f k =g k h k k IN k REF k C g C •OD   k REF I k+1 k IN CF h C   k k REF I k+1 IN k REF k IN C •F C f= C •OD C    I(k+1) k k F OD   k  n n n I k+1 PROP k k k k=1 k=1 k=1 F t = f g h OD Review from last lecture
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Elmore Delay Calculations L x 0 V IN R L V OUT x 1 x 2 x 3 t=0 V IN t=0 V(x 1 ) t=0 V(x 2 ) t=0 V(x 3 ) t t t t X 1 <X 2 <X 3 For Review from last lecture
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Elmore Delay Calculations • It can be shown that this is a reasonably good approximation to the actual delay • Numbering is critical (resistors and capacitors numbered from input to output) • As stated, only applies to this specific structure ni PD i j i=1 j=1 t = C R     R 1 C 1 R 2 C 2 R 3 C 3 R n C n V IN V OUT Elmore delay: Review from last lecture
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Elmore Delay Calculations 4i PD i j i=1 j=1 t = C R     Elmore delay: R 1 C 1 V IN R 1 R 2 C 2 V IN V 1 V 2 R 1 R 2 R 3 C 3 V IN V 3 R 1 R 2 R 3 R 4 C 4 V IN V 4 1 1 1 t =R C 2 1 2 2 t = R R C 3 1 2 3 3 t = R R R C  4 1 2 3 4 4 t = R R R +R C R 1 C 1 R 2 C 2 R 3 C 3 R 4 C 4 V IN V OUT V 1 V 2 V 3 V 4 Example: What is really happening?   4 PD i i=1 t = t Creating 4 first-order circuits Delay to V 1 , V 2 , V 3 and V 4 calculated separately by considering capacitors one at a time and assuming others are 0 where 1 2 3 4 i i i j j=1 t =C R , , , j Review from last lecture
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Power Dissipation in Logic Circuits V DD F A PDN PUN I DD 1 1 , 1 () CL tT AVG T DD DD CL t P V I t dt T Assume current periodic with period T CL Review from last lecture
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Power Dissipation in Logic Circuits Types of Power Dissipation • Static • Pipe • Dynamic • Leakage - Gate - Diffusion - Drain Review from last lecture
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Static Power Dissipation HL STAT,AVG P +P P= 2 If Boolean output averages H and L 50% of the time V DD F A PDN PUN I DD ) DD DDH DDL STAT,AVG V (I + I 2 Generally decreases with V DD I DDH =I DDL =0 for static CMOS gates so P STAT =0 Review from last lecture
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Pipe Power Dissipation Due to conduction of both PUN and PDN during transitions V DD F A PDN PUN I DD Can be made small if transitions are fast Usually negligible in Static CMOS circuits
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Dynamic Power Dissipation Due to charging and discharging C L on logic transitions V DD F A PDN PUN
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EE 330 Lect 44 Fall - EE 330 Lecture 44 Digital Circuits Power Dissipation Other Logic Styles High Frequency Device Models Review from last lecture

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