EE 435 Lect 39 Spring 2010

EE 435 Lect 39 Spring 2010 - EE 435 Lecture 39 ADC Design...

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EE 435 Lecture 39 ADC Design
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Data Converter Type Chart Speed Resolution 4 8 12 16 20 24 1K 10K 100K 1M 10M 100M 1G 10G Oversampled Nyquist .• •• Review from last lecture .•
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ADC Types Flash Pipeline Two-Step Flash Multi-Step Flash Cyclic (algorithmic) Successive Approximation Folded Dual Slope Single-bit Multi-bit First-order Higher-order Continuous-time Nyquist Rate Over-Sampled .• •• Review from last lecture .•
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Nyqyist Rate Usage Structures Speed Resolution 4 8 12 16 20 1K 10K 100K 1M 10M 100M 1G 10G Flash Pipeline SAR .• •• Review from last lecture .•
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SAR ADC • DAC Controller may be simply U/D counter • SAR ADC will have no missing codes if DAC is monotone • Not very fast but can be small V IN DAC n C LK DAC Controller V REF .• •• Review from last lecture .•
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Flash ADC 2 n : n Encoder n R R R R R V REF V IN X OUT d k CL .• •• Review from last lecture .•
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Clocked Comparator V IN Φ 2 Φ 2 V REF V DACk Φ 1 Φ 1 d k Regenerative Comparators Differential Single-Ended Regenerative Feedback Large offset voltage (100mV or more)
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Flash ADC with Front-End S/H S/H ADC Flash X IN n X OUT C LK
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Flash ADC Summary Flash ADC Very fast Simple structure Usually Clocked Bubble Removal Important Seldom over 6 or 7 bits of resolution
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Clocked Comparator V DACk Φ 1 Φ 1 Φ 2A C 1 V IN V OUT Preamplifier with offset compensation Ideally removes all offset effects May not have a large enough gain Regenerative latch often used
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Clocked Comparator V DACk Φ 1 Φ 1 Φ 2A C 1 V IN V OUT Preamplifier with offset compensation and regenerative latch V DACk Φ 1 Φ 1 Φ 2A C 1 V IN V OUT Gain of preamplifier may still not be large enough
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Flash ADC Summary Flash ADC Very fast Simple structure Usually Clocked Bubble Removal Important Seldom over 6 or 7 bits of resolution Flash ADC has some really desirable properties (simple and fast) Wouldn’t it be nice if we could derive most of the benefits of the FLASH ADC without the major limitations Number of comparators increases geometrically --- 2 n To be practical at higher resolution, must address the major limitation of the FLASH ADC Major Limitation of FLASH ADC at higher resolutions?
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ADC Types Flash Pipeline Two-Step Flash Multi-Step Flash Cyclic (algorithmic) Successive Approximation Folded Dual Slope Single-bit Multi-bit First-order Higher-order
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This note was uploaded on 01/31/2012 for the course EE 345 taught by Professor Geiger during the Fall '11 term at Iowa State.

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EE 435 Lect 39 Spring 2010 - EE 435 Lecture 39 ADC Design...

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