ECE 320 Lab 7 - UL

ECE 320 Lab 7 - UL - Experiment #7 NMOS Logic Inverter...

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Experiment #7 NMOS Logic Inverter Amplifier with Enhancement Transistor Load Executive Summary: In this lab a CD4007 was used as a load for VN106. Due to the characteristic of an enhancement mode MOSFET, it works as an inverter. The voltage that is being inputted through the gate creates a channel between the drain and source. As a result, current starts to flow through the drain to source. As the current flows we don’t get any voltage at V O , The threshold voltage to create the channel between the drain-source is about 1.6v. This is the turn on voltage. Before this voltage no current flows through the transistor and we get the V DD at V o . from the threshold voltage to about 2V, drop is linear. In this region we used the transistor as an amplifier. We chose the bias point at 1.85 volts from the graph. At this point, the transistor’s gain was -10.86. The maximum gain can be obtained from this transistor was -16.11 because the bias point was increased to 1.88V. The output impedance of this transistor was about 699.2
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ECE 320 Lab 7 - UL - Experiment #7 NMOS Logic Inverter...

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