The Memory Management Unit

The Memory Management Unit - The value of the page table...

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The Memory Management Unit CPU Memory Cache Memory Management Unit (MMU) Translation Look- Aside Buffer (TLB) Page Table Register Page Table RAM I/O Address Bus Data Bus VM Address Physical (hardware) Address
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The Memory Management Unit The MMU has a Page Table Register that points to the current page table that will be used for the translation. Each process has a its own page table. The page table register is updated during a context switch from one process to the other. The page table has the information of the memory ranges that are valid in a process
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The Memory Management Unit
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Unformatted text preview: The value of the page table register changes every time time there is a context switch from one process to another. Consecutive pages in Virtual memory may correspond to non-consecutive pages in physical memory. The Memory Management Unit To prevent looking up the page table at every memory access, the most recent translations are stored in the Translation Look-Aside buffer (TLB). The TLB speeds up the translation from virtual to physical memory addresses. A page fault is an interrupt generated by the MMU...
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This note was uploaded on 01/30/2012 for the course CS 354 taught by Professor Staff during the Fall '08 term at Purdue University-West Lafayette.

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The Memory Management Unit - The value of the page table...

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