301Syllabus - CECS 301 Computer Logic Design II 2012 R. W....

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CECS 301 Computer Logic Design II © 2012 R. W. Allison 301 Syllabus -- Page 1 CECS 301 – Computer Logic Design II (Spring 2012) California State University, Long Beach College Of Engineering Department of Computer Engineering and Computer Science Instructor: R. W. Allison Office : ECS 504 M-W : 1:00 to 2:00 T-Th : 2:30 to 3:30 Telephone : (562) 985-8034 Email : rallison@csulb.edu WWW : http://www.cecs.csulb.edu/~rallison Grading : Midtem1 -- 20% Midterm 2 -- 20% Final Exam -- 25% Lab Assignments – 20% H omework and Quizzes -- 15% Above median: A's and B's. Below median: C's, D's and F's. Tentative Course Outlin e Week Topics 1 5 Basic Digital Functions. Sequential Logic and State Machines. Verilog Structural and Behavior Models. Programmable Logic Devices. Midterm 1. 6 10 State Machines II. FPGA architecture. Sequential timing analysis. Memory technologies. Midterm 2. 11 15 ALU and Datapath design. Introduction to RTL, micro-operations, microinstructions and Control Unit design. Processor architecture; pipelining. Review. Final Exam. Topics:Sequential logic, FPGA designs, basic Arithmetic Logic Unit (ALU) design, memory devices. Laboratory projects with FPGA implementations using industry standard Electronic Design and Automation (EDA) tools. Textbook and Materials “Fundamentals of Digital Logic with Verilog Design,” by Brown and Vranesic (2 nd Edition/McGraw Hill) “CECS 301 – Computer Logic Design II,” by R. W. Allison (CD available from the Instructor) “Digilent Nexys 2 Prototyping Board” — www.digilentinc.com “Xilinx ISE WebPack (12.x) Software” - www.xilinx.com/support/download/index.htm Prerequisites CECS 174. Pre or Co-requisite: CECS 311 or EE 331
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CECS 301 Computer Logic Design II © 2012 R. W. Allison 301 Syllabus -- Page 2 Homework and Quizzes Homework will be assigned from both the textbook and from instructor designed problems. The purpose of the homework is to help constitute the student with the important, and sometimes difficult, concepts related to lectures and/or assigned reading. Note: due dates will be given when homework is assigned -- absolutely no late homework will be accepted. “Pop quizzes” will be given to help solidify lecture/reading material. Lab Assignments The due dates for each lab assignment will be announced when assigned. Students should plan ahead for difficulties and not put off working on the assignments until the last minute. I strongly suggest that you start to work on your lab assignments as soon as you receive them. The secret to success is putting some careful work “up front,” solidifying your design, and finishing it as soon as possible. The philosophy of this class is to prepare you for the "real world" environment. In the "real world" you are rewarded for meeting the schedules set up by management and frowned upon when you are the case of a schedule slip. Thus, late lab assignments will suffer heavy penalization (5% per day).
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This note was uploaded on 02/01/2012 for the course VLSI 1012 taught by Professor Paul during the Spring '11 term at Hanover.

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301Syllabus - CECS 301 Computer Logic Design II 2012 R. W....

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